Semiconductor package having thermal interface material (TIM)

Details Semiconductor package having thermal interface material (TIM) Semiconductor package having thermal interface material (TIM)

2006-07-25

2006-07-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C257SE23101

Reexamination Certificate

active

07081375

ABSTRACT:
A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

REFERENCES:
patent: 5298791 (1994-03-01), Liberty et al.
patent: 5658831 (1997-08-01), Layton et al.
patent: 5747102 (1998-05-01), Smith et al.
patent: 6245186 (2001-06-01), Alcoe et al.
patent: 6396700 (2002-05-01), Chu et al.
patent: 6409073 (2002-06-01), Kaskoun et al.
patent: 6437240 (2002-08-01), Smith
patent: 6486499 (2002-11-01), Krames et al.
patent: 03-068157 (1991-03-01), None
English language abstract of Japanese Publication No. 03-068157.

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