Semiconductor package having resin substrate with recess and...

Details Semiconductor package having resin substrate with recess and... Semiconductor package having resin substrate with recess and...

2011-03-01

2011-03-01

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S686000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

07898075

ABSTRACT:
In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

REFERENCES:
patent: 4961105 (1990-10-01), Yamamoto
patent: 7435910 (2008-10-01), Sakamoto et al.
patent: 2001-068796 (2001-03-01), None
patent: 2001-274324 (2001-10-01), None
patent: 2005-0117715 (2005-12-01), None
English language abstract of Japanese Publication No. 2001-274324.
English language abstract of Japanese Publication No. 2001-068796.
English language abstract of Korea Publication No. 2005-0117715.

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