Semiconductor package having reduced thickness

Details Semiconductor package having reduced thickness Semiconductor package having reduced thickness

2006-10-03

2006-10-03

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000, C257S676000

Reexamination Certificate

active

07115445

ABSTRACT:
A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25–75% of the thickness of the leads.

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