Semiconductor package having non-aligned active vias

Details Semiconductor package having non-aligned active vias Semiconductor package having non-aligned active vias

2011-01-11

2011-01-11

Nguyen, Thinh T (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S776000, C257S781000, C257SE23062, C438S629000, C438S637000

Reexamination Certificate

active

07868459

ABSTRACT:
A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

REFERENCES:
patent: 6313537 (2001-11-01), Lee et al.
patent: 6542352 (2003-04-01), Devoe et al.
patent: 6900395 (2005-05-01), Jozwiak et al.
patent: 2001/0010407 (2001-08-01), Ker et al.

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