Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1998-12-31
2001-03-13
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S686000, C257S738000, C257S777000, C257S780000, C257S783000, C257S790000
Reexamination Certificate
active
06201302
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor package, and more specifically, to a package having multiple dies formed therein.
BACKGROUND OF THE INVENTION
Integrated circuits manufactures are constantly striving to reduce semiconductor device sizes. With the rapid advances in wafer fabrication process technology, IC designers are always tempted to increase chip level integration at an ever faster pace. It has been the trend in integrated circuit (IC) technology to make small, high speed and high density devices. Thus, the density of semiconductor devices per unit area of silicon wafer is increased. It follows then that the semiconductor devices, such as transistors and capacitors, must be made smaller and smaller.
In recent years, there has existed a high interest of developing the ball grid array (BGA) package and assembly technology. It is because that the renewed desire in high density hybrid is driven by the requirement of larger numbers of electrical connections, the increasing clock rate of digital systems. However, a conventional lead frame package meets an obstacle to increase the number of the package's lead. Thus, the requirement of the operation speed is limited by such packages. The industry has moved away from the use of pins as connectors for the semiconductor package due to the aforesaid reason and the limitation on the input/output pins. As a result, solder ball have been used to meet the present and further demand, one of such solder ball electrical connection technologies is known as ball grid array (BGA) semiconductor package that is superior to pins. The BGA offers many advantages over conventional packages such as solder ball I/O and high speed due to a short path for signal transformation.
As well known in the art, the BGA package includes a substrate with a semiconductordie formed thereon. A plurality of bond pads are mounted to the top surface of the substrate. Gold wires are electrically connected these bond pads to a plurality of conductive traces formed on the substrate. The conductive traces each terminate with a pad where a solder ball is attached. Typically, an encapsulating material covers the die and the substrate for preventing the moisture. One of such BGA is disclosed in U.S. Pat. No. 5,640,047. In the package, solder balls
24
,
25
are connected with a printed wiring board. The surface of the ground plane
22
is made of copper leaf that is covered by a second dielectric layer
26
. The first and second outer connecting terminal lands
21
,
23
that are exposed to atmosphere by means of flux. A semiconductor die
32
is mounted by using a conductive adhering agent
31
. Electrode pads mounted on the die
32
are connected to the wire bonding portions
18
.
A further BGA package is developed by Motorola, which can be seen in U.S. Pat. No. 5,583,377. The package
10
includes circuitized substrate
12
having a plurality of conductive traces
14
formed thereon. Conductive pads
16
are formed on the bottom surface of the substrate
12
. The electrical signal is routed from the substrate
12
to the die
13
by using wires
19
. The conductive pads
16
and solder balls
21
are formed in a matrix configuration for external signal accessing to the die
13
. A plurality of vias
18
are extended through the substrate
12
for electrical coupling. The device
10
also has a heat sink
22
having a cavity for receiving the die
13
.
However, none of the aforementioned packages can receive multiple semiconductor dies in the device. Thus, what is required is a package having multiple semiconductor dies receiving therein.
SUMMARY OF THE INVENTION
The package is a semiconductor package that includes a substrate having an opening approximately formed in the central portion. A first die is mounted on a die receiving area on the upper surface of the substrate by using electrically nonconductive attaching material. Preferably, the first die is precisely over the opening and the first die is coupled to conductive traces on the substrate via bonding wires. A second die is attached at the lower side surface of the first die by epoxy. The first and the second die can be selected from the IC, microprocessor or chip. The second die is electrically coupled to the conductive traces on the substrate by bonding wires. The first die and a portion of the substrate are encapsulated by using mold compound. A heat sink can be optionally positioned in the mold compound to spread the heat generated by the dies. An encapsulant is filled in the opening and covers the second die, bonding wires. A plurality of solder balls that are electrically connected with a printed circuit board are mounted on the substrate. Preferably, the solder balls are configured in a matrix configuration. The solder balls are connected with the printed circuit board so as to establish a thermal and electrical connection. The modified embodiment is also possible to use a conductive plate, such as metal plate between the first and second dies. Preferably, the conductive plate is made of cooper.
The third embodiment according to the present invention includes a multi-layer substrate. Apertures are respectively formed in the layers of the substrate and are enlarged from the layer under the uppermost layer to the lowermost layer. The apertures form in combination a cavity. Conductive traces are formed on the surface of the multi-layer substrate. A first die is attached on the top surface of the uppermost layer of the multi-layer substrate and is electrically connected to the conductive traces by using bonding wires. A second die is received in the cavity and attached on the bottom surface of the uppermost layer of the substrate. Similarly, the second die is electrically connected to the conductive traces on the substrate by using bonding wires. Mold compound covers the first die and a portion of the substrate to prevent the die, bonding wires from moisture or external force. A heat sink is optionally located on the top of the multi-layer substrate to spread heat. A cap is attached to the lower surface of the multi-layer substrate. A encapsulant is filled in the cavity. Solder balls are arranged on the lower surface of the multi-layer substrate for communicating with external modules.
REFERENCES:
patent: 5578869 (1996-11-01), Hoffman et al.
patent: 5696666 (1997-12-01), Miles et al.
patent: 5760478 (1998-06-01), Bozso et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 5949135 (1999-09-01), Washida et al.
patent: 5963429 (1999-10-01), Chen
patent: 2-126685 (1990-05-01), None
“Reworkable Chip-On-Board Package”, IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, pp. 1433 and 1444.
Chambliss Alonzo
Chaudhuri Olik
Sampo Semiconductor Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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