Semiconductor package having isolated inner lead

Details Semiconductor package having isolated inner lead Semiconductor package having isolated inner lead

2008-11-24

2011-11-01

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S668000, C257S692000, C257S735000, C257SE23037

Reexamination Certificate

active

08049339

ABSTRACT:
A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking.

REFERENCES:
patent: 5206536 (1993-04-01), Lim
patent: 6593649 (2003-07-01), Lin et al.
patent: 6984878 (2006-01-01), Park et al.
patent: 7592691 (2009-09-01), Corisis et al.
patent: 2005/0189643 (2005-09-01), Zhou et al.
patent: 2005/0236698 (2005-10-01), Ozawa et al.
patent: I287876 (2007-01-01), None

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