Semiconductor package having adjacently arranged semiconductor c

Details Semiconductor package having adjacently arranged semiconductor c Semiconductor package having adjacently arranged semiconductor c

1994-08-29

1996-09-24

Kincaid, Kristine L.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

257673, 361760, H01L 2302

Patent

active

055593054

ABSTRACT:
A single stacked semiconductor package has at least two semiconductor chips densely mounted via a lead on chip method for attaching leads of a lead frame by alternately arranging the leads over or under the semiconductor chips. A tape automated bonding method using thin metal leads formed on insulating tapes, and an adhesive coated on the lower portions of the leads to mount at least two semiconductor chips can also be used. A stacked semiconductor device manufacturing method and the semiconductor package according thereto are suitable for use in large scale integration circuits.

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patent: 4937656 (1990-06-01), Kohara
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5206536 (1993-04-01), Lim
patent: 5245215 (1993-09-01), Sawaya
patent: 5296737 (1994-03-01), Nishimura et al.
patent: 5303120 (1994-04-01), Michii et al.
patent: 5334803 (1994-08-01), Yamamura et al.
patent: 5349233 (1994-09-01), Sasaki
patent: 5358904 (1994-10-01), Murakami et al.

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