Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2006-02-14
2006-02-14
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S692000, C257S737000, C257S792000
Reexamination Certificate
active
06998720
ABSTRACT:
Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.
REFERENCES:
patent: 6611052 (2003-08-01), Poo et al.
patent: 6617237 (2003-09-01), Tong et al.
patent: 6709980 (2004-03-01), Gleason
patent: 2003/0025202 (2003-02-01), Mikagi et al.
patent: 2003/0133274 (2003-07-01), Chen et al.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Vu Hung
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