Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-11-02
2004-01-06
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S691000, C257S329000, C257S328000
Reexamination Certificate
active
06674157
ABSTRACT:
BACKGROUND OF THE INVENTION
Embodiments of the invention are directed semiconductor packages, and in particular to semiconductor packages for radio frequency (RF) circuit applications.
Radio frequency (RF) amplifiers are used in wireless communication networks. In recent years, the operating frequencies of wireless networks have increased and are now into the gigahertz (GHz) frequencies. At such high frequencies, power transistors have been used in RF power amplification devices, e.g., in antenna base stations.
A simplified illustration of a portion of an LDMOS RF power transistor package is shown in FIG.
1
.
FIG. 1
shows a semiconductor die
11
with an N+ source region
12
and an N+ drain region
17
at the top surface. The source region
12
electrically connects to a source electrode S at the bottom surface of the semiconductor die
11
. A P+ region
14
provides a conductive path to the N+ source region
12
. A metal portion
18
shorts out a p+ body region
19
and the N+ source region
12
to provide an electrical path between the source region
12
to the source electrode S. A drain electrode D and a gate G are also at the top surface of the semiconductor die
11
. For clarity of illustration, the gate oxide corresponding to the gate G is not shown in FIG.
1
. The source electrode S at bottom surface of semiconductor die
11
is attached to a metallic substrate
13
. The metallic substrate
13
serves as both a heat sink and a ground reference for the source electrode S. Wires (not shown) are coupled to the gate electrode G and the drain electrode D to provide the semiconductor die
11
with input and output connections. In operation, source current flows from the metallic substrate
13
, laterally through the drift region
16
to the drain region
17
, and out of the semiconductor die
11
to a wire (not shown) coupled to the drain electrode D.
RF power transistors generate a significant amount of heat. For example, 50% efficiency is not a typical of class A amplifiers. For high output power applications (e.g., more than 60 Watts), special packaging is required to remove heat from the power transistor to prevent overheating and further loss of efficiency. Overheating can also degrade the operational characteristics of a power transistor. For some applications, it is desirable to keep the temperature of the semiconductor die in an RF package to less than 100° C. during operation.
To address the heat problem, some have reduced the thickness of the semiconductor die (e.g., to about 4-5 mils) using conventional wafer thinning processes (e.g., lapping). Reducing the amount of semiconductor material in the die also reduces the amount of heat retained by the semiconductor die. While decreasing the thickness of a semiconductor die causes it to retain less heat, a thinner semiconductor die can undesirably lead to a decrease in the breakdown voltage of the transistor.
Embodiments of the invention address these and other problems.
SUMMARY OF THE INVENTION
Embodiments of the invention are directed to semiconductor die packages.
One embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface; a source region at the first surface of the semiconductor die; a gate at the first surface of the semiconductor die; a drain region at the second surface of the semiconductor die; a ground plane proximate the second surface and distal to the first surface; and a bus member covering a portion of the first surface of the semiconductor die and having at least one leg, wherein the bus member electrically couples the source region of the semiconductor die to the ground plane.
Another embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface; a source region at the first surface of the semiconductor die; a gate at the first surface of the semiconductor die; a drain region at the second surface of the semiconductor die; a ground plane proximate the second surface and distal to the first surface; a conductive layer between the ground plane and the semiconductor die; an isolator layer disposed between the conductive layer and the ground plane; a bus member covering a major portion of the first surface of the semiconductor die and electrically coupling the source region of the semiconductor die to the ground plane; a carrier enclosing the semiconductor die and the bus member; a drain lead passing through the carrier; a first electrical conductor coupling the drain lead to the conductive layer and the drain region; a gate lead passing through the carrier; and a second electrical conductor coupling the gate lead to the gate.
Another embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a vertical power transistor, wherein the semiconductor die has a first surface and a second surface; an emitter region at the first surface of the semiconductor die; a base region at the first surface of the semiconductor die; a collector region at the second surface of the semiconductor die; a ground plane proximate the second surface and distal to the first surface; and a bus member covering a portion of the first surface of the semiconductor die and having at least one leg, wherein the bus member electrically couples the emitter region of the semiconductor die to the ground plane.
Another embodiment of the invention is directed to a semiconductor die package comprising: a semiconductor die comprising a transistor, wherein the semiconductor die has a first surface and a second surface; a source region in the semiconductor die; a gate in the semiconductor die; a drain region in the semiconductor die; a ground plane proximate the second surface and distal to the first surface; and a bus member covering a portion of the first surface of the semiconductor die and having at least one leg, wherein the bus member electrically couples the source region of the semiconductor die to the ground plane.
These and other embodiments can be described with reference to the foregoing Figures and Detailed Description.
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Cruz Lourdes
Cuneo Kamand
Fairchild Semiconductor Corporation
Townsend and Townsend / and Crew LLP
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