Semiconductor package and stack arrangement thereof

Details Semiconductor package and stack arrangement thereof Semiconductor package and stack arrangement thereof

2006-05-03

2008-08-05

Tran, Minh-Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S668000, C257S676000, C257S685000, C257S686000, C257S701000, C257S702000, C257S704000, C257S734000, C257S735000, C257SE23031, C257SE23038, C257SE23039, C257SE23061, C257SE23085

Reexamination Certificate

active

07408244

ABSTRACT:
A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

REFERENCES:
patent: 5814883 (1998-09-01), Sawai et al.
patent: 5939779 (1999-08-01), Kim
patent: 6002170 (1999-12-01), Kim et al.
patent: 6605866 (2003-08-01), Crowley et al.
patent: 6649834 (2003-11-01), Hsieh et al.
patent: 6876068 (2005-04-01), Lee et al.
patent: 7045396 (2006-05-01), Crowley et al.
patent: 2005/0098879 (2005-05-01), Kim

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