Semiconductor package and multi-chip semiconductor package...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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C257S777000, C257S773000, C257S786000, C257SE23141

Reexamination Certificate

active

07825504

ABSTRACT:
Disclosed is a semiconductor package and a multi-chip semiconductor package. The semiconductor package includes a semiconductor chip having bonding pads located at a center portion thereof; redistribution patterns extending from the bonding pads toward one edge of the semiconductor chip; and dummy bump pads located adjacent to another edge of the semiconductor chip which is opposite the one edge.

REFERENCES:
patent: 6696765 (2004-02-01), Kazama et al.
patent: 6969908 (2005-11-01), Yamaguchi
patent: 7132742 (2006-11-01), Yamaguchi
patent: 7298042 (2007-11-01), Yamaguchi
patent: 2004/0124520 (2004-07-01), Rinne
patent: 2006/0001156 (2006-01-01), Wakiyama et al.
patent: 2007/0018336 (2007-01-01), Farnworth et al.
patent: 2007/0029673 (2007-02-01), Yamaguchi
patent: 2007/0102800 (2007-05-01), Kang
patent: 2007/0222054 (2007-09-01), Hembree
patent: 2008/0001276 (2008-01-01), Lee et al.
patent: 20010063236 (2001-07-01), None
patent: 20020030891 (2002-04-01), None
patent: 1020040092304 (2004-11-01), None

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