Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-11-19
2002-09-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S787000
Reexamination Certificate
active
06448633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lead frame with lead separation preventing means, a semiconductor package using the lead frame, and a method for fabricating the semiconductor package. More particularly, the present invention relates to a lead frame having a lead separation preventing means provided at a free end of each inner lead and adapted to increase a bonding force of the inner lead to a resin encapsulate encapsulating the lead frame to fabricate a semiconductor package, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. The present invention also relates to the semiconductor package fabricated using the lead frame, and a fabrication method for the semiconductor package.
2. Description of the Prior Art
In pace with the recent trend of electronic appliances, such as electronic products for domestic and official purposes, communication appliances, and computers, toward a compactness and high performance, semiconductor packages, which are used for such electronic appliances, have been required to have a compact, highly multi-pinned, light, simple structure.
Such a requirement for semiconductor packages has resulted in developments of semiconductor packages having a structure in which the lower surface of each lead is exposed at the bottom of the resin encapsulate. For such semiconductor packages, there are bottom lead type semiconductor packages and lead end grid array type semiconductor packages. Currently, the demand of semiconductor packages having such a structure is being increased.
Similarly to typical quad-flat or bi-flat type semiconductor packages, such bottom lead type or lead end grid array type semiconductor packages can be fabricated using a well-known method. This method may involve a sawing step for cutting a wafer formed with a plurality of semiconductor chip units into pieces respectively corresponding to those semiconductor chip units, thereby separating the semiconductor chip units from one another, a semiconductor chip mounting step for mounting the semiconductor chip units on respective paddles of lead frame units integrally formed on a lead frame strip by means of a thermally-conductive adhesive resin, a wire bonding step for electrically connecting a free end of each inner lead, included in each lead frame unit, to an associated one of input/output terminals of the semiconductor chip unit mounted on the lead frame unit, a resin encapsulate molding step for molding a resin encapsulate adapted to encapsulate each semiconductor chip unit and a bonding region including bonding wires for the semiconductor chip unit, using encapsulating resin, for the protection of those elements from external environments, thereby forming semiconductor packages each including one semiconductor chip unit and one lead frame unit, a singulation step for cutting inner portions of dam bars of each lead frame unit, thereby separating the semiconductor packages from one another, and a marking step for marking characters or signs on the surface of the resin encapsulate included in each semiconductor package. In the fabrication of quad-flat or bi-flat semiconductor packages, a lead forming step is involved to form leads outwardly protruded by a considerable length from a resin encapsulate into a particular terminal shape, for example, a “J” shape. In the fabrication of bottom lead type or lead end grid array type semiconductor packages, however, it is typically unnecessary to use such a lead forming step. In bottom lead type or lead end grid array type semiconductor packages, the lower surface or free end of each lead is exposed at the bottom of the resin encapsulate. Accordingly, the exposed portion of each lead may be directly used as an external input/output terminal or attached with a solder ball to be used as an external input/output terminal.
A typical structure of such quad-flat or bi-flat semiconductor packages is illustrated in a cross-sectional view of FIG.
9
. Now, this structure will be described in brief in conjunction with FIG.
9
. In
FIG. 9
, the reference numeral
1
′ denotes a semiconductor package having a quad-flat or bi-flat structure. As shown in
FIG. 9
, this semiconductor package includes a semiconductor chip
2
bonded to a paddle
16
by means of a thermally-conductive epoxy resin
32
, and a plurality of leads
11
arranged at each of four sides or two facing sides of the paddle
16
in such a fashion that they are spaced apart from the associated side of the paddle
16
while extending perpendicularly to the associated side of the paddle
16
. The semiconductor package also includes a plurality of conductive wires
3
for electrically connecting the inner leads
12
to the semiconductor chip
2
, respectively, and a resin encapsulate
4
for encapsulating the semiconductor chip
2
and conductive wires
3
. The semiconductor package further includes outer leads
13
extending outwardly from the inner leads
12
, respectively. Each outer lead
13
has a particular shape, for example, a “J” shape, so that it is used as an input/output terminal in a state in which the semiconductor package is mounted on a mother board.
FIGS. 10A and 10B
are, respectively, a plan view illustrating a conventional lead frame and a cross-sectional view illustrating a bottom lead type semiconductor package fabricated using the lead frame, respectively.
As shown in
FIG. 10A
, the lead frame, which is denoted by the reference numeral
10
′, includes a paddle
16
, tie bars
15
for supporting respective comers of the paddle
16
, a plurality of leads
11
arranged at each of four sides of the paddle
16
in such a fashion that they extend perpendicularly to the associated side of the paddle
16
, and dam bars
17
for supporting the leads
11
and tie bars
15
. Each lead
11
has an inner lead
12
encapsulated by a resin encapsulate (shown by phantom lines
21
in
FIG. 10A
) to be subsequently formed, and an outer lead
13
extending outwardly from the resin encapsulate. Dotted lines
23
inside the dam bars
17
represent singulation lines along which the lead frame
10
′ is cut after completing a semiconductor chip mounting process, a wire bonding process, and a resin encapsulate molding process. In
FIG. 10A
, the reference numeral
18
denotes side rails.
The bottom lead type semiconductor package denoted by the reference numeral
1
″ in
FIG. 10B
is that fabricated using the lead frame of FIG.
10
A. As shown in
FIG. 10B
, the semiconductor package
1
″ includes a semiconductor chip
2
bonded to the paddle
16
of the lead frame
10
′, along with the leads
11
of the lead frame
10
′. As mentioned above, the leads
11
are arranged at each of four sides of the paddle
16
while being spaced apart from the associated side of the paddle
16
by a desired distance. The semiconductor package
1
″ also includes conductive wires
3
for electrically connecting the inner leads to the semiconductor chip
2
, and a resin encapsulate
4
for encapsulating the semiconductor chip
2
and conductive wires
3
. The outer lead
13
of each lead
11
has a length shorter than that of a typical quad-flat semiconductor package. Typically, the outer lead of each lead
11
is not subjected to any forming process. The lower surface of each inner lead
12
is exposed at the bottom of the resin encapsulate
4
, so that it serves as an external input/output terminal, along with the lower surface of the associated outer lead
13
.
In the above mentioned bottom lead type semiconductor package
1
″, however, the inner leads
12
, which are encapsulated in the resin encapsulate
4
in such a fashion that their lower surfaces are exposed, have a planar structure having a simple rectangular shape or an end-rounded rectangular shape. By virtue of such a planar structure of the inner leads
12
, there is a high possibility for the leads
11
to be separated from the resin encapsu
Chung Young Suk
Davis Terry
Han Chung Suk
Ku Jae Hun
Kwak Jae Sung
Amkor Technology Inc.
Nhu David
Stetina Brunda Garred & Brucker
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