Semiconductor package and method for manufacturing the same

Details Semiconductor package and method for manufacturing the same Semiconductor package and method for manufacturing the same

2007-10-29

2009-11-17

Dang, Phuc T (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S700000, C257S701000, C361S760000, C361S765000

Reexamination Certificate

active

07619316

ABSTRACT:
A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

REFERENCES:
patent: 7307852 (2007-12-01), Inagaki et al.
patent: 7462784 (2008-12-01), Kariya et al.
patent: 2005/0029658 (2005-02-01), Sugiyama et al.
patent: 2006/0175083 (2006-08-01), Muramatsu et al.
patent: 2001-007250 (2001-01-01), None

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