Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-06-12
2004-03-23
Niebling, John (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S118000, C438S126000, C257S777000
Reexamination Certificate
active
06709894
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabrication methods of the same, and more particularly, to a stack semiconductor package, and a method for fabricating the stack semiconductor package in a batch manner.
BACKGROUND OF THE INVENTION
For improving performances and functionality of electronic products, a semiconductor package is preferably highly integrated with more electronic components being incorporated on a fixed-sized chip. However, forming of a highly integrated chip requires considerably advanced fabrication technology, which thereby sets limitation to process availability and application for producing highly integrated chips. Therefore, an alternative way is to develop a multi-chip semiconductor package.
A multi-chip semiconductor package e.g. a stack package is characterized by stacking at least two chips on a chip carrier such as substrate or lead frame. The stack semiconductor package can be fabricated by process steps illustrated in
FIGS. 4A
to
4
C. Referring to
FIG. 4A
, the first step is to mount a plurality of first chips
22
on a chip carrier
20
, and to form a plurality of bonding wires
23
for electrically connecting the first chips
22
respectively to the chip carrier
20
. Then, referring to
FIG. 4B
, an adhesive
212
such as silver paste or epoxy resin is applied on the first chips
22
, for allowing a plurality of second chips
25
to be respectively stacked on the first chips
22
, with the adhesive
212
being interposed between the first and second chips
22
,
25
; this forms a duel-chip stack structure. Finally, referring to
FIG. 4C
, a plurality of second bonding wires
26
are formed to electrically connect the second chips
25
respectively to the chip carrier
20
; then, molding, ball-implanting and singulating processes are performed to form a plurality of individual semiconductor packages
2
.
In the above package fabrication method, for stacking the second chips
25
on the first chips
22
, a conventional dispensing process is performed to apply the adhesive
212
on the first chips
22
; the dispensing process can be implemented by stamping or globing technique in a manner that, a syringe
27
filled with the adhesive
212
is moved to and fro along the chip carrier
20
; when the syringe
27
moves to a pre-determined position right above a first chip
22
, the adhesive
212
is released and applied on the first chip
22
. However, such a one-by-one adhesive-applying method is considerably time-consuming, and not suitably used for batch package production. Moreover, adhesive-dispensing equipment is usually expensive, making fabrication costs undesirably increased. Furthermore, due to amount variations of the adhesive
212
being applied on different first chips
22
, it is therefore difficult to maintain uniform qualities of fabricated products.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a semiconductor package and a method for fabricating the same, whereby adhesive layers respectively applied on chips are simultaneously formed in a batch manner, without having to use expensive adhesive-dispensing equipment, thereby making fabrication costs and time both significantly reduced.
Another objective of the invention is to provide a semiconductor package and a method for fabricating the same, allowing adhesive layers to be uniformly applied on chips respectively, thereby improving quality of fabricated package products.
In accordance with the above and other objectives, a method for fabricating a semiconductor package proposed in the invention, comprises the steps of: preparing a substrate plate having a plurality of arrayed substrates; mounting at least one first chip on each of the substrates of the substrate plate, wherein the first chip has an active surface and an inactive surface opposed to the active surface, allowing the inactive surface to be attached to the substrate; forming a plurality of first bonding wires for electrically connecting the active surfaces of the first chips respectively to the substrates; mounting on the substrate plate a shielding structure having a supporting portion adapted to abut against the substrate plate without affecting arrangement of the first chips and the first bonding wires, and a shielding portion attached to the supporting portion for being elevated by the supporting portion to a predetermined height that prevents the shielding portion from interfering with the first bonding wires, wherein the supporting portion is formed with a plurality of arrayed receiving holes for receiving the first chips and the first bonding wires, and the shielding portion is formed with a plurality of openings each connecting a corresponding one of the receiving holes, and wherein the shielding structure is dimensioned sufficiently in surface area to cover the first chips, and each of the openings of the shielding portion is smaller in dimension than each of the receiving holes of the supporting portion; applying an adhesive onto the active surface of each of the first chips via the openings of the shielding portion of the shielding structure in a batch manner, so as to form an adhesive layer on the active surface of each of the first chips; removing the shielding structure from the substrate plate, and stacking at least one second chip on the adhesive layer; electrically connecting the second chips to the substrate plate by wire bonding with a plurality of second bonding wires; and performing molding, ball-implanting and singulating processes to form a plurality of individual semiconductor packages.
The above fabrication method is characterized by using a shielding structure as a barrier for adhesive application. The shielding structure is composed of a shielding portion and a supporting portion, wherein the shielding portion is supported above a substrate plate by the supporting portion, and formed with a plurality of openings respectively corresponding in position to first chips mounted on the substrate plate. This allows an adhesive to be applied through the openings of the shielding portion and form adhesive layers respectively on active surfaces of the first chips. These adhesive layers can be desirably made with uniform thickness, allowing overall structure to be evenly dimensioned in height with second chips being stacked on the first chips by the adhesive layers, thereby improving quality of fabricated package products. And, forming of the adhesive layers is implemented in a batch manner by e.g. printing technique, thereby making fabrication costs and time effectively reduced, without having to use expensive adhesive-dispensing equipment and conventional dispensing technique for applying an adhesive on underlying chips one by one.
REFERENCES:
patent: 6316289 (2001-11-01), Chung
patent: 6352879 (2002-03-01), Fukui et al.
patent: 6620649 (2003-09-01), Uchida
Shan Wei-Heng
Su Huan-Ping
Tsai Chung-Che
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Niebling John
Roman Angel
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