Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-12-14
2002-04-09
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S781000, C257S784000, C257S786000, C257S723000
Reexamination Certificate
active
06369454
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip size semiconductor package and a method for fabricating such a chip size semiconductor package. More particularly, the present invention relates to a chip size semiconductor package having a thin structure fabricated by interconnecting at least two adjacent semiconductor chip units of a wafer including a plurality of semiconductor chip units by use of bonding wires, molding encapsulates on the upper surface of the wafer to completely encapsulate the bonding wires, conducting a singulation process for the wafer in such a fashion that cut ends of the bonding wires formed during the singulation process are exposed at one or more side surfaces of the encapsulate encapsulating those bonding wires. The present invention also relates to a method for fabricating this chip size semiconductor package.
2. Description of the Prior Art
Generally, semiconductor packages are classified into a variety of types in accordance with the structures thereof. In particular, semiconductor packages are classified into an in-line type and a surface mount type in accordance with the mounting structures thereof. For representative in-line type semiconductor packages, there are a dual in-line package (DIP) and a pin grid array (PGA) package. For representative surface mount type semiconductor packages, there are a quad flat package (QFP) and a ball grid array (BGA) package.
Recently, use of surface mount type semiconductor packages has increased, as compared to in-line type semiconductor packages, in order to obtain an increased element mounting density of a printed circuit board meeting a compactness or miniature of electronic appliances. A representative example of such surface mount type semiconductor packages will be described in conjunction with
FIGS. 1A and 1B
.
Referring to
FIG. 1A
, a conventional surface mount type semiconductor package is illustrated. As shown in
FIG. 1A
, the conventional semiconductor package includes a semiconductor chip
10
with integrated electronic circuits, a mounting plate
30
for mounting the semiconductor chip
10
thereon by means of an adhesive layer
20
interposed therebetween, a plurality of leads
40
for externally transmitting signals from the semiconductor chip
10
, bonding wires
50
for interconnecting the semiconductor chip
10
with the leads
40
, and an encapsulate
60
for encapsulating the semiconductor chip and other elements of the semiconductor package, thereby protecting those elements from mechanically, electrically, and chemically harmful environments.
Referring to
FIG. 1B
, a method for fabricating the conventional semiconductor package having the above mentioned configuration is illustrated. This method involves a lead frame preparation step for preparing a lead frame (not shown) integrally formed with the paddle
30
and leads
40
, a semiconductor chip mounting step for forming the adhesive layer
20
on the paddle
30
of the lead frame, and attaching the semiconductor chip
10
to the paddle
30
, a wire bonding step for connecting the semiconductor chip
10
to the leads
40
of the lead frame by means of electrically conductive wires
50
, an encapsulating step for molding an encapsulate resin to form an encapsulate adapted to encapsulate the semiconductor chip
10
and conductive wires
50
, a plating step for plating portions of the leads
40
outwardly exposed from the encapsulate
60
, and a trimming and forming step for bending and cutting the leads
40
into a desired shape.
The above mentioned conventional semiconductor package has a size considerably larger than that of the semiconductor chip used. For this reason, this semiconductor package cannot meet the recent demand for a light, thin, simple, miniature structure. There is also a limitation in increasing the number of output terminals. This is because there is a limitation in reducing the lead width and the pitch of adjacent leads. For this reason, the conventional semiconductor package has a relatively small number of output terminals. As a result, it is impossible for the conventional semiconductor package to meet the recent demand for a highly integrated miniature structure. Furthermore, the fabrication method used to fabricate the conventional semiconductor package involves a relatively large number of processes. For this reason, there is a limitation in reducing the costs through use of simplified processes.
SUMMARY OF THE INVENTION
Therefore, a first object of the invention is to provide a chip size semiconductor package having a simple and thin structure including an increased number of output terminals.
A second object of the invention is to provide a chip size semiconductor package assembly including a plurality of chip size semiconductor packages assembled in the form of a wafer, which has a simple and thin structure including an increased number of output terminals.
A third object of the invention is to provide a method for fabricating a chip size semiconductor package having a thin structure, which is capable of simplifying the processes used, thereby reducing the costs.
The first object of the present invention is accomplished by providing a chip size semiconductor package comprising a semiconductor chip having a plurality of pads, bonding wires each bonded at one-side end thereof to an associated one of the pads of the semiconductor chip, and an encapsulate for encapsulating the bonding wires and an upper surface of the semiconductor chip, wherein: the other-side ends of the bonding wires are exposed at one or more side surfaces of the encapsulate so that they serve as output terminals, respectively.
The second object of the present invention is accomplished by providing a chip size semiconductor package assembly comprising: a wafer including a plurality of semiconductor chip units each having a plurality of pads; bonding wires for electrically connecting the pads of each of the semiconductor chip units to the pads of at least one of the semiconductor chip units arranged adjacent to the semiconductor chip unit; and encapsulates for encapsulating the bonding wires and an upper surface of the wafer.
The third object of the present invention is accomplished by providing A method for fabricating a chip size semiconductor package comprising the steps of: a wire bonding step for interconnecting at least two adjacent semiconductor chip units of a wafer including a plurality of semiconductor chip units by use of bonding wires, respectively; an encapsulate molding step for molding encapsulates on an upper surface of the wafer, on which the adjacent semiconductor chip units are interconnected by the bonding wires, in such a fashion that the bonding wires are completely encapsulated; and a singulation step for cutting the encapsulate-molded wafer into the individual semiconductor chip units in such a fashion that each of the bonding wires has two cut ends each exposed at a side surface of an associated one of the encapsulates under the condition in which the cut ends of the bonding wires encapsulated in each of the encapsulates are exposed at one or more side surface of the encapsulate.
REFERENCES:
patent: 5856915 (1999-01-01), Weinberg
patent: 5866952 (1999-02-01), Wojnarowski et al.
patent: 5869905 (1999-02-01), Takebe
patent: 5973263 (1999-10-01), Tuttle et al.
patent: 5987739 (1999-11-01), Lake
patent: 6072239 (2000-06-01), Yoneda et al.
patent: 6197616 (2001-03-01), Hyoudo et al.
patent: 6294100 (2001-09-01), Fan et al.
patent: 6309909 (2001-10-01), Ohgiyama
Amkor Technology Inc.
Clark Jhihan B
Parsons James E.
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