Semiconductor package and method

Details Semiconductor package and method Semiconductor package and method

2005-01-20

2009-12-22

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With bumps on ends of lead fingers to connect to semiconductor

C257SE23046, C257SE23124, C257SE23039, C257SE23051, C257SE21513, C257S778000, C257S796000, C257S684000, C257S696000, C257S737000, C257S738000, C257S784000, C257S786000, C257S787000, C257S676000, C257S666000, C257S670000, C257S674000, C438S123000

Reexamination Certificate

active

07635910

ABSTRACT:
A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.

REFERENCES:
patent: 5172214 (1992-12-01), Casto
patent: 5648682 (1997-07-01), Nakazawa et al.
patent: 6212079 (2001-04-01), Balakrishnan et al.
patent: 6242798 (2001-06-01), Cha et al.
patent: 6469398 (2002-10-01), Hori
patent: 6587357 (2003-07-01), Halamik et al.
patent: 6723585 (2004-04-01), Tu et al.
patent: 6876087 (2005-04-01), Ho et al.
patent: 2003/0116833 (2003-06-01), Lee et al.

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