Semiconductor package and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S678000, C257S684000, C257S687000, C257S701000, C257S702000, C257S704000, C257S658000, C257S666000, C257S667000, C257S685000, C257S688000, C257S689000, C257S693000, C257S773000, C257S775000, C257S777000, C257S788000, C257S774000, C257S004000, C257S048000, C257SE23005, C257SE23007, C257SE27064, C257SE27086, C257SE27094, C257SE25006, C257SE25013, C257SE21021, C257SE25027, C257SE21614

Reexamination Certificate

active

07847384

ABSTRACT:
A semiconductor package100is constructed of a semiconductor chip110, a sealing resin106for sealing this semiconductor chip110, and wiring105formed inside the sealing resin106. And, the wiring105is constructed of pattern wiring105bconnected to the semiconductor chip110and also formed so as to be exposed to a lower surface106bof the sealing resin106, and a post part105aformed so as to extend in a thickness direction of the sealing resin106, the post part in which one end is connected to the pattern wiring105band also the other end is formed so as to be exposed to an upper surface106aof the sealing resin106.

REFERENCES:
patent: 5726493 (1998-03-01), Yamashita et al.
patent: 5747874 (1998-05-01), Seki et al.
patent: 6740964 (2004-05-01), Sasaki
patent: 2002/0112884 (2002-08-01), Tanaka
patent: 2006/0186524 (2006-08-01), Aiba et al.
patent: 2002-158312 (2002-05-01), None
patent: 2004-031650 (2004-01-01), None
patent: 2005-217225 (2005-08-01), None

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