Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1998-10-14
2002-09-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S787000, C257S788000, C257S790000, C257S795000, C257S737000, C257S778000
Reexamination Certificate
active
06448665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices such as semiconductor packages, particularly relates to thin and highly reliable semiconductor packages.
2. Description of the Related Art
As electronic instruments become compact, development of a technology packaging various kinds of electronic components in high density into electronic instruments is being in progress. Further, upon packaging the electronic components with high density, the electronic components such as semiconductor packages and the like are desired to be made smaller and thinner. This is because, in order to realize a compact and highly functional electronic instrument, not only improvement of integration of a semiconductor element but also compactness of a semiconductor package in which a semiconductor element is packaged are required. In order to correspond to such a requirement, various types of thin semiconductor packages are being proposed.
A means for mounting a semiconductor element on a wiring substrate can be generally divided into a face-up type bonding (wire bonding), and face-down type bonding (flip chip bonding).
In the face-up type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with bonding wires. Then, by molding the semiconductor element including the bonding wires on the wiring substrate, a semiconductor package is formed.
On the other hand, in the face-down type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with conductive bumps and the like.
In the semiconductor package of the flip chip type, there are an over-coat type in which a semiconductor element is molded as a whole, and a bare chip type in which a semiconductor element is exposed. Even in the latter case, it is generally done to seal a gap between a semiconductor element and a wiring substrate with a resin and the like. Semiconductor packages of the flip chip type, because they can be made thinner than those of the face-up type, are recently used much in CSP(Chip Size Package) and the like. The CSPs are used much in, for instance, computers, semiconductor packages of high frequency and integrated function used in communication instruments, or portable information instruments such as a PDA.
FIG. 11
is a diagram showing a structure of a conventional semiconductor package.
In the semiconductor package
90
illustrated in
FIG. 11
, a semiconductor element (chip)
92
is mounted in a face-down manner on a wiring substrate
91
. Connecting terminals
92
a
of the semiconductor element
92
and pads
93
disposed on the wiring substrate
91
are connected with conductive bumps
94
. The conductive bumps are composed of, for instance, solder, gold and the like.
Further, a gap between the wiring substrate
91
and the semiconductor element
92
is sealed with a resin layer
95
called an under-fill. Here, a semiconductor package of a structure in which a rear surface of the semiconductor
92
is exposed is illustrated, however, if the semiconductor element
92
is covered with a molding resin as a whole, a semiconductor package of the over-coat structure can be obtained.
Further, on the rear surface of the semiconductor mounting surface of the wiring substrate
91
, connecting pads
96
connected to the bonding pads
93
are disposed, on the connecting pads
96
solder balls
97
are disposed. Those solder balls
97
and the conductive bumps
94
are connected electrically with interior wiring.
In the wiring substrate
91
, glass fabric based epoxy resin is employed as an insulating layer. As the wiring substrate
91
, that of two-layered structure is employed here, however, that of multi-layered structure such as three-layered structure or more may be employed. Further, on the rear surface (upper surface) of the semiconductor chip, a metallic cap or a heat-sink is disposed in some cases.
Further, the solder balls are disposed as BGA (ball grid array) type terminals. Incidentally, the connecting terminals
96
to which the solder balls
97
are disposed and the bonding pads
93
of the wiring substrate are connected between layers with, for instance, through holes, conductive pillars consisting of conductive resin and the like.
FIG. 12A
, FIG.
12
B and
FIG. 12C
are diagrams explaining a method forming a resin layer
95
(under-fill).
First, on the circumference of a semiconductor element
92
, a liquid resin
95
i
such as epoxy resin or the like is supplied from a dispense nozzle
99
. Viscosity of the resin is selected and adjusted according to demands. The dispense nozzle
99
is attached to a syringe in which the resin
95
i
is stocked. The resin
95
i
permeates into a gap between the wiring substrate
91
and the semiconductor element
92
due to capillary action (FIG.
12
A). That is, the resin
95
i
supplied from the dispense nozzle
99
is dripped on the circumference of the wiring substrate
91
(FIG.
12
B), then the dripped resin permeates into the gap between the wiring substrate
91
and the semiconductor element
92
(FIG.
12
C), thus the under-fill is formed thereby.
However, such a thin semiconductor package as described above has a problem described in the following. That is, in order to reduce thickness of a semiconductor package as a whole, strength is sacrificed, accordingly the semiconductor package is liable to suffer deformation such as warp and the like.
When such a warp of the semiconductor package occurs, the connecting terminals
96
and the solder balls
97
constituting the BGA, for instance, are not arranged on the same plane, to deteriorate so-called coplanarity. Therefore, there occur such problems that a semiconductor package is made impossible to be packaged on a mother board, or, even after packaging, in the course of time, due to the added thermal load and the like, reliability of connection can not be maintained. Therefore, in the case of a thin semiconductor package being used actually, how to improve productivity and reliability is a problem to be solved.
In the manufacturing steps of a semiconductor package of flip-chip type such as aforementioned, in the step of forming a resin layer
95
, the liquid resin is cured thermally in the temperature range of 100 to 180° C. Therefore, in the course of returning to room temperature, the semiconductor package suffers warp.
Thermal expansion coefficient of a semiconductor element and that of a wiring substrate differ approximately one digit in general. The thermal expansion coefficient of a semiconductor element (chip) consisting of silicon, for instance, is about 3-4 ppm/K, whereas the thermal expansion coefficient of a wiring substrate having an organic insulating layer such as FR-
4
, FR-
5
or BT resin (Bis maleimide triazine) is about 12 to 20 ppm/K. Therefore, deformation due to thermal load is larger for the wiring substrate than that of the semiconductor chip. Therefore, stress pulling the semiconductor element
92
occurs, due to this stress, the semiconductor package suffers warp.
FIG. 13A
, FIG.
13
B and
FIG. 13C
are diagrams explaining stress suffered by a semiconductor package. Here, appearance of chip crack and resin crack observed in TCT (Thermal Cycle Test) which is a generally adopted environment test of semiconductor package is shown schematically.
In this test, a so-called fan-in type semiconductor package, in which a wiring substrate
91
is smaller than a semiconductor element
92
, was employed.
On a wiring substrate
91
is mounted a semiconductor element
92
, a resin layer
95
is filled in a gap formed between the wiring substrate
91
and the semiconductor element. In general, compared with thicknesses of the wiring substrate
91
and semiconductor element
92
, that of an under-fill resin layer
95
is extremely thin.
When the aforementioned thermal load is added on such a semiconductor package, on the rear surface side of the semiconductor element
92
a tensile stress works, due to this stress chip crack occurs
Nakazawa Takahito
Sugizaki Yoshiaki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Nadav Ori
Thomas Tom
LandOfFree
Semiconductor package and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2866608