Semiconductor package and fabrication process thereof

Details Semiconductor package and fabrication process thereof Semiconductor package and fabrication process thereof

2006-10-10

2008-10-07

Smith, Matthew S. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S787000, C257SE21499, C257SE23060, C438S108000, C438S127000

Reexamination Certificate

active

07432601

ABSTRACT:
A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

REFERENCES:
patent: 5679977 (1997-10-01), Khandros et al.
patent: 6628526 (2003-09-01), Oshima et al.
patent: 2004/0041279 (2004-03-01), Fuller et al.

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