Semiconductor package and fabrication method

Details Semiconductor package and fabrication method Semiconductor package and fabrication method

1996-11-14

1999-02-02

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

257783, 257780, H01L 2348, H01L 2352, H01L 2940

Patent

active

058669507

ABSTRACT:
A semiconductor package comprises a circuit board having a wiring circuit including at least a connecting portion, the wiring circuit being formed on a first main surface of the circuit board, a semiconductor chip mounted on the first main surface of the circuit board on face-down basis, an insulation resin layer filled in a space between the semiconductor chip and the circuit board, and a flat-type external connecting terminal electrically connected to the semiconductor chip and formed and exposed to a second main surface of the circuit board.

REFERENCES:
patent: 3495133 (1970-02-01), Miller
patent: 3887760 (1975-06-01), Krieger et al.
patent: 3923231 (1975-12-01), Catalano et al.
patent: 4961105 (1990-10-01), Yamamoto
patent: 4962415 (1990-10-01), Yamamoto et al.
patent: 5203076 (1993-04-01), Banerji et al.
patent: 5350947 (1994-09-01), Takekawa et al.
patent: 5407864 (1995-04-01), Kim
Tasao Soqa et al., "Development of a High-Reliability Flip-Chip Packaging Reinforced by Resin," 433b Electronics and Communications in Japan, Part 2: Electronics, vol. 71, No. 11, pp. 19-27, (Dec. 1988) (New York).
J. Clementi et al., "Flip-Chip Encapsulation on Ceramic Substrates," 43rd Electronic Components & Technology Conference, pp. 175-181, Jun. 1-4, 1993.
"Direct Chip Bonding For Liquid Crystal Display," IBM Technical Disclosure Bulletin, vol. 34, No. 5, pp. 183-184, Oct. 1991.

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