Semiconductor package

Details Semiconductor package Semiconductor package

2000-07-25

2003-08-26

Dinkins, Anthony (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C174S050510, C257S670000, C257S676000

Reexamination Certificate

active

06610924

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a lead frame package, and more specifically to a leadless semiconductor package.
2. Description of the Related Art
Lead frame packages has been used for a long period of time in the IC packaging history mainly because of its low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both faster and smaller in size, the traditional lead frame packages become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former was widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages, for examples, CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile, package weight are major concerns.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a chip scale and low profile solution due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both foot print and package profile can be greatly reduced.
FIG. 1
shows a bottom view of a leadless package
100
wherein the leads
110
a
are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad
110
b
of the leadless package
100
is exposed from the bottom of the package thereby providing better power dissipation. Typically, there are four tie bars
100
c
connected to the die pad
110
b.
Due to elimination of the outer leads, leadless packages feature lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package
100
very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
Conventional leadless packaging process comprises the following steps.
Firstly, a polyimide (PI) tape was attached to the bottom of a lead frame, this is to prevent the mold flash problem in the molding process. Typically, a lead frame (denoted as
105
in
FIG. 2
) for used in the MAP (mold array package) molding process comprises a plurality of units
110
each including a plurality of leads
110
a
arranged at the periphery of a die pad
110
b
. Each die pad
10
b
is connected to the lead frame
105
by four tie bars
110
c.
Then, referring to
FIG. 3
, IC chips
120
are attached to the die pads
110
b
using silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is used to make interconnections between the silicon chips
120
and the leads
110
a
of the lead frame
105
. After wire bonding, the lead frame
105
and the chips
120
attached thereon are encapsulated in a package body
130
. Typically, a MAP molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process.
The molded product is then marked with either laser or traditional ink. Finally, postmold curing and singulation steps were conducted to complete the packaging process. Typically, the mark either formed by laser or ink printing is adapted to be identified by a recognition system which provides all the coordinates of the leads needed in the following testing or trouble-shooting process. Since there is no recognizable mark at the bottom of the leadless package before the marking step, it is hard to avoid human error during manual operation. Furthermore, the mark formed by laser or ink printing may become faint due to scratching in the delivery thereby changing the contour of the mark such that it becomes unrecognizable.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to overcome the problems and disadvantages associated with the above-described technique.
It is another object of the present invention to provide a leadless semiconductor package comprising a plurality of tie bars connecting to a die pad wherein the package is characterized in that all the tie bars are embedded in a package body except a part of at least one tie bar or an odd number of tie bars exposed from the lower surface of the package to work as an indicial mark.
It is another object of the present invention to provide a leadframe for use in forming leadless semiconductor packages, the lead frame comprising a plurality of units each adapted for use in packaging a semiconductor chip, wherein the lead frame is characterized in that each unit is provided with at least one tie bar or an odd number of tie bars each having a bulge portion work as an indicial mark thereby significantly reducing human error during packaging steps performed before the marking step.
In accordance with the above listed and other objects we discloses- a leadless semiconductor package mainly comprising a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. Each tie bar extends from a comer of the die pad to a corresponding comer of the leadless semiconductor package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the backside surface of the leads is exposed from the lower surface of the leadless semiconductor package. The leadless semiconductor package of the present invention is characterized in that all the tie bars are embedded in the package body except a part of at least one tie bar or an odd number of tie bars exposed from the lower surface of the leadless semiconductor package to work as an indicial mark.
The present invention further provides a lead frame for use in forming leadless semiconductor packages. The lead frame comprises a plurality of units each having four corners. Each unit includes a die pad adapted for receiving a semiconductor chip and a plurality of leads arranged at the periphery of the die pad. Each of the die pads is connected to the lead frame by a plurality of tie bars wherein at least one tie bar or an odd number of tie bars each has a bulge portion formed with a thickness substantially equal to the thickness of the die pad and the leads. The thickness of all tie bars of each unit is substantially less than the thickness of the lead frame except the bulge portion or bulge portions thereof whereby the bulge portion or bulge portions work as an indicial mark thereby significantly reducing human error during packaging steps performed before the marking step.


REFERENCES:
patent: 4855807 (1989-08-01), Yamaji et al.
patent: 5894108 (1999-04-01), Mostafazadeh et al.
patent: 6177718 (2001-01-01), Kozono

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