Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-01-24
2002-04-23
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S787000, C257S666000, C257S793000
Reexamination Certificate
active
06376905
ABSTRACT:
BACKGROUND OF THE INVENTION
i) Field of the Invention
The present invention relates to a resin encapsulated semiconductor package using a lead frame.
ii) Description of Related Art
Conventionally, a lead frame of a resin encapsulated semiconductor package uses a 42 Ni-Fe alloy or a copper alloy.
For example, quad flat packages (QFP) such as application specific integrated circuits (ASIC) and microcomputers entail large power dissipation and so use a lead frame of a copper alloy. Thin small outline packages (TSOP) mounting thereon memory devices such as a dynamic random access memory (DRAM), a static random access memory (SRAM) or the like, which are large in generation of heat and size are mounted, use a 42 Ni-Fe alloy. Also, a quad flat nonleaded package (QFN), a SOP and a QFP, which mount thereon an IC for electric power, generally uses a lead frame formed of a copper alloy.
Linear expansion coefficients of parts constituting a resin encapsulated semiconductor package are significantly different from one another such that a copper alloy used as a frame material has a linear expansion coefficient of 17×10
−6
/° C., a 42 Ni-Fe alloy has a linear expansion coefficient of 4×10
−6
to 5×10
−6
/° C., silicon as a semiconductor device has a linear expansion coefficient of 3×10
−6
/° C., and a molding or encapsulating resin has a linear expansion coefficient of 12 to 25×10
−6
/° C. Thus thermal stresses generate inside the semiconductor package in a cooling process after a resin molding or encapsulating process, in a temperature cycle test for testing reliability. In the temperature cycle test, such thermal stresses apply repeatedly to thereby cause fatigue crack in a resin from an end of a die pad or a lead frame, or a bonding wire is sometimes disconnected due to fatigue. Also, the temperature cycle test after packaging of a substrate or repetition of ON/OFF in electronic equipments may cause fatigue failure in solder joints of leads due to differences in linear expansion coefficient between the semiconductor package and the packaged substrate.
Differences in linear expansion coefficient between a frame material and a semiconductor device are such that a 42 Ni-Fe alloy has a smaller difference and a smaller thermal stress generated than a copper alloy does. Therefore, only replacement into a copper alloy as a lead frame material with a view to enhancement in heat conduction from a semiconductor package will lead to increased thermal stresses and an increased possibility of generation of the above-mentioned fatigue failure, and so making the sacrifice of heat conduction in some measure a conventional 42 Ni-Fe alloy has been recently used in memory TSOPs having an increased heat dissipation and a large chip size. Also, in microcomputers having a relatively large chip size and a high power dissipation and high pin counts QFPs mounting thereon ASICs, a copper alloy based lead frame has been used which is small in self inductance to be suited to the high frequency operation, and high in heat conducting properties. However, when a solder used in small chips and having a large thermal conductivity is used to bond a device to a lead frame, solder fatigue occurs to deteriorate bonding, so that only an epoxy based bonding material (silver paste or the like) having a low Young's modulus has been used.
In recent small-sized portable electronic equipments, small-sized semiconductor devices have multiplied which are of a structure called a chip scale package (CSP) and adopt electric connection with solder bumps arranged in a matrix configuration. CSPs have a large volume ratio of a device in a semiconductor package, and an apparent linear expansion coefficient close to that of the device. Therefore, with packaged substrates of small-sized portable equipments with a large number of CSPs mounted thereon, it has become general to use a low thermal expansion substrate, in which a conventional linear expansion coefficient of 15 to 16×10
−6
/° C. is reduced to about half, that is, 8×10
−6
/° C. However, with resin encapsulated semiconductor devices for mixed loading on a low expansion substrate and making use of a conventional lead frame using a copper alloy, there is a fear of reduction in life of solder joints and generation of resin crack because of an increased difference in linear expansion coefficient between the devices and the substrate.
SUMMARY OF THE INVENTION
An object of the present invention is to solve at least one of the aforementioned problems, and to provide a resin encapsulated semiconductor package, which ensures reliability on strength and has high heat conducting properties.
The object of the present invention is attained, for example, by constituting a resin encapsulated semiconductor package in the following manner. That is to say, used as a material for a lead frame is a material composed mainly of a composite alloy of Cu
2
O and Cu (having largest contents among materials constituting leads), which is sintered to have a thermal conductivity comparable to that of a copper alloy conventionally used and a smaller linear expansion coefficient than that of the copper alloy. A range where physical properties of the Cu/Cu
2
O composite alloy are examined is 20 to 80 vol. % in terms of a compounding ratio of Cu
2
O, and involves 280 to 41 W/(mK) of thermal conductivity and 13.8 to 5.5×10
−6
/° C. of linear expansion coefficient. For example, in the case where there is a need of a thermal conductivity of 150 W/(mK) or more comparable to that of a copper alloy used in semiconductor devices with a view to high heat conduction, the compounding ratio of Cu
2
O suffices to be set to 20 to 46%. In this case, the linear expansion coefficient of the Cu/Cu
2
O composite alloy amounts to about 13.8 to 10.5×10
−6
/° C., and approximates to 3×10
−6
/° C. of linear expansion coefficient of a chip as compared with 17×10
−6
/° C. of linear expansion coefficient of a copper alloy. However, in the case where there is a need of a linear expansion coefficient of 4 to 5×10
−6
/° C. comparable to that of 42 alloy for the sake of stress relaxation, making a compounding ratio of Cu
2
O in the Cu/Cu
2
O composite alloy 80% results in 5.5×10
−6
/° C. of linear expansion coefficient, and 41 W/(mK) of thermal conductivity. Such value is 2.7 times 15 W/(mK) of thermal conductivity of a 42 alloy. In this manner, it suffices to freely adjust the compounding ratio in accordance with an object.
REFERENCES:
patent: 5023698 (1991-06-01), Kobayashi et al.
patent: 5-67713 (1993-03-01), None
patent: 9-148509 (1997-06-01), None
patent: 9-199655 (1997-07-01), None
Tanaka et al., “Thermal Analysis of Plastic QFP with High Thermal Dissipation”, 1992, IEEE, pp. 332-339.
Hisano Nae
Miura Hideo
Antonelli Terry Stout & Kraus LLP
Clark Jhihan B
Hitachi , Ltd.
LandOfFree
Semiconductor package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2891147