Semiconductor package

Details Semiconductor package Semiconductor package

2000-01-03

2002-05-28

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S696000, C257S698000, C257S735000, C257S007000, C257S724000, C257S728000, C257S401000, C257S139000, C257S329000, C257S334000, C257S341000, C257S691000, C257S675000, C257S796000

Reexamination Certificate

active

06396127

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor package in which a semiconductor die is disposed between upper and lower plate members and, more particularly, to an SO
8
semiconductor package in which a source of a MOSFET semiconductor die is electrically coupled to a leadframe via an upper plate member while the MOSFET gate is electrically coupled to the leadframe via a wire bond.
2. Related Art
With reference to
FIG. 1
, a semiconductor package
10
according to the prior art is shown. The semiconductor package
10
includes a bottom plate portion
13
and terminals
12
a
,
12
b
. A semiconductor die
16
is disposed on top of the bottom plate portion
13
and fastened thereto, typically using an epoxy material. The semiconductor die
16
includes a metalized region
18
(typically aluminum) defining a connection area for a top surface of the semiconductor die
16
. Portions of the terminals
12
a
,
12
b
, bottom plate portion
13
, and semiconductor die
16
are encapsulated in a housing
22
, typically formed from a moldable material. In order to obtain an electrical connection between the metalized region
18
and the terminal(s)
12
b
, one or more wires
20
are ultrasonically bonded at one end
21
a
to the metalized region
18
and at a distal end
21
b
to the terminal
12
b.
FIG. 2
shows another semiconductor package
100
of the prior art. In order to electrically connect the metalized region
18
with the terminal
12
b
, one or more wires
24
are stitch bonded at locations
23
, thereby providing additional paths for current to flow from the semiconductor die
16
to the terminal
12
b
. This marginally reduces the resistance of the current path from the semiconductor die
16
to the terminal
12
b.
It is desirable to significantly reduce the resistance and inductance of current paths through a power semiconductor package in order to ensure optimum performance of the semiconductor device. Unfortunately, the semiconductor packages of the prior art do not fully achieve this objective because, among other things, the distance D between one area of the metalized region
18
and the end
21
a
of the wires
20
increases the resistance of the current path from the metalized region
18
to the terminal
12
b
. This problem is exacerbated when the thickness of the metalized region
18
is relatively small (typically, the thickness is approximately 4 to 8 microns). The relatively thin metalized region
18
in combination with the distance D and the cross sectional profile of the wire bond
20
results in a relatively high resistance and inductance for the current path therethrough.
In some packages (for example SO8 packages) the distance D is approximately 80 to 100 mils resulting in a resistance of between about 0.79 and 1.58 mohms for the metalized region
18
. The diameters of the wires
20
,
24
are approximately 2 mils yielding resistances of about 1.05 mohms (when
14
wires are used). With terminal and epoxy resistances aggregating to about 0.307 mohms, such packages exhibit total resistances of between about 2.14 to 2.93 mohms. The resulting package thermal resistance, RJA, can reach 62.5° C./W.
When the semiconductor package
10
includes, for example, a MOSFET semiconductor die
16
, the resistance caused by the distance D and the relatively small diameter of the wires
20
,
24
adds to the overall resistance of the MOSFET. Indeed, when die
16
is a MOSFET die, the terminals
12
a
are typically coupled to the drain of the MOSFET while the terminals
12
b
are coupled to the source of the MOSFET via one or more wire bonds
20
. As ON resistances of MOSFET dies become smaller and smaller, the resistance caused by the distance D and the wire bonds
20
,
24
become a larger and larger portion of the overall resistance from one terminal
12
a
to another terminal
12
b
. Of course, the high frequency performance of a semiconductor device, like a MOSFET, is significantly effected by the resistance and inductance from terminal to terminal through the device.
Some prior art packages have incorporated a large metal strap to obtain an electrical connection between the metalized region
18
and terminal
12
b
. Unfortunately, this technique has only been possible in large semiconductor packages having relatively simple surface structures, such as bipolar junction transistors, diodes, and thyristors. Further, the metal straps were not practical in small outline packages (such as S08, surface mount dual in line packages).
The use of a large metal strap in a MOS-gated device, such as a MOSFET, has not heretofore been achieved because such devices have relatively complex surface structures. In particular, MOS-gated devices typically include a gate runner (or bus), disposed on the surface of the semiconductor die, which traverses the surface such that gate potential is distributed over the surface of the die. Consequently, disposing a large metal strap over the surface of the die has been problematic because the gate runner restricts access to the die surface and could be shorted to the metal strap. Thus, the use of metal straps in MOS-gated semiconductor devices has been prohibitive.
Accordingly, there is a need in the art for a new semiconductor package which overcomes the deficiencies in the prior art semiconductor packages by, among other things, reducing the resistances of the current paths through MOS-gated devices and reducing the inductances of such current paths.
SUMMARY OF THE INVENTION
In order to overcome the deficiencies of the prior art, a semiconductor package according to one aspect of the instant invention includes a power semiconductor package, comprising: a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion;
at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a conductive plate coupled to and spanning a substantial part of the first metalized region defining the source connection, the conductive plate including a periphery and at least one chamfered edge at the periphery extending upward and away from the first metalized region; and at least one beam portion being sized and shaped to couple the conductive plate portion to the at least one second terminal such that it is electrically coupled to the source.
According to another aspect of the invention, the package includes: a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal;
a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a conductive plate coupled to and spanning a substantial part of the first metalized region defining the source connection, a periphery of the conductive plate being defined by a plurality of peripheral edges which circumscribe top and bottom surfaces of the conductive plate; at least one of a plurality of depressions and elongate slots disposed in at least one of the top and bottom surfaces of the conductive plate; at least one beam portion being sized and shaped to couple the conductive plate portion to the at least one second terminal such that it is electrically coupled to the source; and a molded housing which substantially encapsulates the bottom leadframe, semiconductor die and conductive plate.


REFERENCES:
patent: 4189342 (1980-02-01), Kock
pa

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