Semiconductor-on-insulator integrated circuit with selectively t

Details Semiconductor-on-insulator integrated circuit with selectively t Semiconductor-on-insulator integrated circuit with selectively t

1994-03-31

1995-05-23

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257347, 257348, 257352, 257353, H01L 3978

Patent

active

054183910

ABSTRACT:
A silicon-on-insulator transistor structure includes a selectively thinned channel region, leaving the source and drain regions relatively thick. The relatively thin channel region provides for full depletion, larger current handling, and thus, faster operation. The relatively thick source and drain regions provide resistance to damage by electrostatic discharge. The transistor structure can be formed from a silicon-on-insulator wafer by performing a light, deep source/drain implant; a shallow, heavy source/drain implant is optionally performed at this stage. Source and drain regions are masked, while the channel regions are etched to the desired channel thickness. After the mask material is removed, a gate oxide can be grown; gates can then be defined. If it has not been performed earlier, the shallow heavy source/drain implant can be performed at this point. In addition, a channel threshold adjust implant can be performed after the channel regions are thinned and before the gates are formed.

REFERENCES:
patent: 5124768 (1992-06-01), Mano et al.
patent: 5246870 (1993-09-01), Merchant
"Double Snapback in SOI nMOSFET's and its Application for SOI ESD Protection," Koen Verhage, Guido Groeseneken, Jean-Pierre Colinge and Herman E. Maes, IEEE Electron Device Letters, vol. 14, No. 7, pp. 326-328 (Jul. 1993).
"MOSFET Drain Engineering for ESD Performance," Y. Wei, Y. Loh, C. Wang and C. Hu, EOS/ESD Symposium 92, 4.3.1-4.3.6. Jan. 1992.

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