Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-11-01
2003-10-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S405000, C438S406000, C438S403000, C438S428000, C438S381000
Reexamination Certificate
active
06635550
ABSTRACT:
TECHNICAL FIELD OF THE INSTITUTION
This invention relates in general to the field of electronic devices and, more particularly, to an improved architecture and method of construction for semiconductor on insulator devices.
BACKGROUND OF THE INVENTION
In a wide variety of applications, integrated electronic devices can be formed in a semiconductor layer which is disposed outwardly from a buried insulator layer. This architecture is commonly referred to as semiconductor on insulator or “SOI” architecture SOI architectures are used in a wide variety of digital, power and RF applications. The buried insulator layer typically comprises a layer of oxide which allows for integrated architectures and especially isolation techniques that are not available in conventional integrated system architectures that are built on monolithic semiconductor substrates.
SOI structures are typically formed using two separate substrates which are bonded together before the device grade semiconductor material is exposed. The ability to form a cohesive and durable bond between the two substrates prior to processing the device layer is critical to the overall practicality of the device. If the bond is subject to delamination for any reason, the reliability of the entire system is degraded.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an SOI architecture that provides for a cohesive substrate to substrate bond. In accordance with the teachings of the present invention, an SOI architecture is provided that allows a cohesive substrate bond that includes the capability to form buried conductive layers within the SOI architecture.
According to one embodiment of the present invention, a method of forming a electronic device is described which comprises forming a buried conductive layer. A layer of semiconductor material is then deposited outwardly from the buried conductive layer. The outer surface of the semiconductor layer can then be bonded to an outer substrate. The bonded architecture can then be processed to expose a device semiconductor layer.
An important technical advantage of the present invention inheres in the fact that the SOI architecture disclosed provides for a buried conductive layer but still provides for a cohesive bond between the buried substrate and the outer device layers associated with the bonded substrate.
According to an alternate embodiment of the present invention, a trench can be formed through the outer layers penetrating into the inner substrate through the buried conductor layer. This trench can then be filled with dielectric material. In this manner, conductive devices can be formed on the outer surface of the dielectric layer which defines a low-loss region. Other active devices which benefit from the buried conductor layer can be formed in non-low-loss regions of the outer surface of this integrated system.
REFERENCES:
patent: 5536361 (1996-07-01), Kondo et al.
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 2003/0075776 (2003-04-01), Ohkubo et al.
Brady III Wade James
Fourson George
Maldonado Julio J.
Tung Yingsheng
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