Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2005-03-15
2005-03-15
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S351000, C257S401000, C257S350000
Reexamination Certificate
active
06867433
ABSTRACT:
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
REFERENCES:
patent: 4314269 (1982-02-01), Fujiki
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4946799 (1990-08-01), Blake et al.
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 6008095 (1999-12-01), Gardner et al.
patent: 6015993 (2000-01-01), Voldman et al.
patent: 6046487 (2000-04-01), Benedict et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6222234 (2001-04-01), Imai
patent: 6232163 (2001-05-01), Voldman et al.
patent: 6258664 (2001-07-01), Reinberg
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6294834 (2001-09-01), Yeh et al.
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6387739 (2002-05-01), Smith, III
patent: 6413802 (2002-07-01), Hu et al.
patent: 6414355 (2002-07-01), An et al.
patent: 6429061 (2002-08-01), Rim
patent: 6448114 (2002-09-01), An et al.
patent: 6475838 (2002-11-01), Bryant et al.
patent: 6475869 (2002-11-01), Yu
patent: 6489664 (2002-12-01), Re et al.
patent: 6524905 (2003-02-01), Yamamichi et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6558998 (2003-05-01), Belleville et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6653700 (2003-11-01), Chau et al.
patent: 6720619 (2004-04-01), Chen et al.
patent: 6762448 (2004-07-01), Lin et al.
patent: 20020076899 (2002-06-01), Skotnicki et al.
patent: 20020153549 (2002-10-01), Laibowitz et al.
patent: 20020190284 (2002-12-01), Murthy et al.
patent: 20030001219 (2003-01-01), Chau et al.
patent: 20030030091 (2003-02-01), Bulsara et al.
patent: 20030080386 (2003-05-01), Ker et al.
patent: 20040026765 (2004-02-01), Currie et al.
patent: WO 0317336 (2003-02-01), None
Matthews, J.W., et al., “Defects in Epitaxial Multilayers—III. Preparation of Almost Perfect Multilayers,” Journal of Crystal Growth, vol. 32, (1976), pp. 265-273.
Schüppen, A., et al., “Mesa and Planar SiGe-HBTs on MBE-Wafers,” Journal of Materials Science: Materials in Electronics, vol. 6, (1995), pp. 298-305.
Matthews, J.W., “Defects Associated with the Accommodation of Misfit Between Crystals,” J. Vac. Sci. Technol., vol. 12, No. 1 (Jan./Feb. 1975), pp. 126-133.
Thompson, S., et al., “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low k ILD, and 1 um2SRAM Cell,” IEDM, pp. 61-64.
Welser, J., et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures,” IEDM 1992, pp. 1000-1002.
Ismail, K, et al., “Electron Transport Properties of Si/SiGe Heterostructures: Measurements and Device Implications,” Applied Physics Letters, vol. 63, No. 5, (Aug. 2, 1993), pp. 660-662.
Nayak, D.K., et al., “Enhancement-Mode Quantum-Well GexSi1-xPMOS,” IEEE Electron Device Letters, vol. 12, No. 4, (Apr. 1991), pp. 154-156.
Gámiz, F., et al., “Strained-Si/SiGe-on-Insulator Inversion Layers: The Role of Strained-Si Layer Thickness on Electron Mobility,” Applied Physics Letters, vol. 80, No. 22, (Jun. 3, 2002), pp. 4160-4162.
Gámiz, F., et al., “Electron Transport in Strained Si Inversion Layers Grown on SiGe-on-Insulator Substrates,” Journal of Applied Physics, vol. 92, No. 1, (Jul. 1, 2002), pp. 288-295.
Mizuno, T., et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1, (Jan. 2002), pp. 7-14.
Tezuka, T., et al., “High-Performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique,” Symposium On VLSI Technology Digest of Technical Papers, (2002), pp. 96-97.
Jurczak, M., et al. “Silicon-on-Nothing (SON)—an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11, (Nov. 2000), pp. 2179-2187.
Jurczak, M., et al., “SON (Silicon on Nothing)—A New Device Architecture for the ULSI Era,” Symposium on VLSI Technology Digest of Technical Papers, (1999), pp. 29-30.
Maiti, C.K., et al., “Film Growth and Material Parameters,” Application of Silicon-Germanium Heterostructure, Institute of Physics Publishing, Ch. 2 (2001) pp. 32-42.
Tiwari, S., et al., “Hole Mobility Improvement in Silicon-on-Insulator and Bulk Silicon Transistors Using Local Strain,” International Electron Device Meeting, (1997), pp. 939-941.
Ootsuka, F., et al., “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Applications,” International Electron Device Meeting, (2000), pp. 575-578.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers—I. Misfit Dislocations,” Journal of Crystal Growth, vol. 27, (1974), pp. 118-125.
Matthews, J.W., et al., “Defects in Epitaxial Multilayers—II. Dislocation Pile-Ups, Threading Dislocations, Slip Lines and Cracks,” Journal of Crystal Growth, vol. 29, (1975), pp. 273-280.
Huang, X., et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electrons Devices, vol. 48, No. 5 (May 2001) pp. 880-886.
Shahidi, G.G., “SOI Technology for the GHz Era,” IBM Journal of Research and Development, vol. 46, No. 2/3 (Mar. 2002) pp. 121-131.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” International Electron Devices Meeting (2001) pp. 433-436.
Wong, H.S.P., “Beyond the Conventional Transistor,” IBM Journal of Research and Development, vol. 46, No. 2/3 (Mar./May 2002) pp. 133-167.
Yang, et al., “25nm CMOS Omega FETs,” International Electron Devices Meeting, Digest of Technical Papers (Feb. 2002) pp. 255-258.
Yang, et al., “35nm CMOS FinFETs,” 2002 Symposium on VLSI Technology Digest of Technical Papers (Jun. 2002) pp. 109-110.
Wang, L.K., et al., “On-Chip Decoupling Capacitor Design to Reduce Switching-Noise-Induced Instability in CMOS/SOI VLSI,” Proceedings of the 1995 IEEE International SOI Conference, Oct. 1995, pp. 100-101.
Yeoh, J.C., et al., “MOS Gated Si:SiGe Quantum Wells Formed by Anodic Oxidation,” Semicond. Sci. Technol. (1998), vol. 13, pp. 1442-1445, IOP Publishing Ltd., UK.
Cavassilas, N., et al., “Capacitance-Voltage Characteristics of Metal-Oxide-Strained Semiconductor Si/SiGe Heterostructures,” Nanotech 2002, vol. 1, pp. 600-603.
Blaauw, D., et al., “Gate Oxide and Subthreshold Leakage Characterization, Analysis and Optimization,” date unknown.
“Future Gate Stack,” International Sematech, 2001 Annual Report.
Chang, L., et al., “Reduction of Direct-Tunneling Gate Leakage Current in Double-Gate and Ultra-Thin Body MOSFETs,” 2001 IEEE, Berkeley, CA.
Chang, L., et al., “Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs,” 2002 IEEE, vol. 49, No. 12, Dec. 2002.
Chen How-Yu
Hu Chenming
Huang Chien-Chao
Lee Wen-Chin
Yang Fu-Liang
Jackson Jerome
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Semiconductor-on-insulator chip incorporating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor-on-insulator chip incorporating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor-on-insulator chip incorporating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3406839