Semiconductor on-chip repair scheme for negative bias...

Details Semiconductor on-chip repair scheme for negative bias... Semiconductor on-chip repair scheme for negative bias...

2008-01-10

2010-11-23

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Temperature

C438S004000, C327S513000

Reexamination Certificate

active

07838958

ABSTRACT:
Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

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Bolam et al., U.S. Appl. No. 12/050,990, Office Action Communication, Mar. 4, 2010, 10 pages.

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