Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-10
2003-09-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S322000, C257S324000, C257S326000, C365S184000
Reexamination Certificate
active
06614070
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improvements in semiconductor memories and, more particularly, to improvements in electrically erasable, electrically programmable read-only memories used for large capacity data storage.
2. Description of the Related Art
The demand for portable and hand held devices which require large amounts of data storage has grown substantially within recent years and is expected to continue to grow well into the next decade. Products such as digital cameras, cellular telephones, personal organizers, voice recording devices and palm top personal computers as well as a host of specialized remote data collection tools are available today and several new products are in development. In nearly all of these products data is stored on solid state electronic media rather than on a hard disk drive, due to the requirements of higher performance, lower energy consumption and superior ruggedness. However, the cost of a given amount of solid state storage media has proven to greatly exceed that of hard disk drive solutions, making it difficult to build attractively priced products which contain enough solid state memory to adequately meet the product requirements.
Recently, a “NAND” type non-volatile memory cell structure has reemerged as a proposed way to reduce manufacturing costs over conventional solid state storage. Higher storage capacity and lower costs are achieved by utilizing a smaller memory cell composed of a single memory transistor which shares each of its nodes with adjacent memory cells. Several such cells are grouped together in a “NAND stack”, with their channels in series, along with means to connect the stack ends to a bit line and a reference line. In the past the non-volatile memory transistor used a MNOS non-volatile element, but more recently, floating gate approaches have dominated. In either case the small cell size is the key element which enable higher densities and lower costs.
However, floating gate NAND cells have not been able to realize expected cost reductions due to inherent limitations. Internal write voltages of floating gate NAND memories are typically five to seven times the normal CMOS product power supply limits. Cells sizes are difficult to scale due to the stacked polysilicon floating gate geometry making manufacturing increasingly difficult. Threshold voltages are difficult to control, causing long test times and lower product yields. Each of these factors are intrinsic to the floating gate NAND approach and each significantly affects the product cost.
In the past MNOS (Metal Nitride Oxide Silicon) NAND memory arrays were proposed as a means to realize lower costs. The MNOS structure is conceptually a better approach than the floating gate method, since it is simpler to manufacture, has a naturally tighter threshold voltage distribution, requires minimal test times, and enables much lower write voltages. However, the methods proposed for reading and writing MNOS NAND memories progressively weakens the stored data, destroying it altogether prior to the expected life of the product. This problem is referred to as a “disturb”.
Referring now to
FIG. 1
, current NAND technologies utilize a single transistor floating gate device
10
. The drain (D), gate (G), source (S), and bulk (B) contacts, as well as the floating gate (FG) are labeled. Current flows in a channel region between the drain and source when the drain and source are at different potentials, and under direct control of the potential placed on the gate relative to the source and bulk, whose potentials need not be equal. The FG is a non-volatile charge storage node isolated from and between the gate and the channel region. To erase a memory cell, a large negative gate to bulk potential is formed that couples the layer FG to a negative potential, causing holes to be accumulated in the channel region. These holes can tunnel to the FG by the Fowler-Nordheim effect, because of the large electric fields that result from the large gate to bulk potential. Holes on the FG will erase the memory cell to shift the threshold in a negative direction to provide a logic “0” stored state.
To program the memory cell, a large positive gate to bulk potential is formed that couples the FG to a positive potential and inverts the channel region with electrons. As with holes, the electrons can tunnel to the FG by the Fowler-Nordheim effect. The threshold voltage of the memory transistor shifts in the positive direction to provide a logic “1” state.
Conventional NAND technologies are designed such that erased memory cells have depletion thresholds and programmed memory cells have enhancement thresholds. More specifically, the depletion state threshold voltage is achieved when the gate voltage is negative with respect to the source node and the enhancement state threshold voltage is achieved when the gate voltage is positive with respect to the source node. When written, these negative and positive thresholds have a fairly broad distributions, typically in the 1.5-2.0 volt range.
A conventional NAND stack
20
is shown in
FIG. 2
, where sixteen (16) non-volatile memory cells
10
(MC
0
-MC
15
) are placed in series with two n-channel select transistors
11
and
12
, transistors
11
being placed at the drain side (MSD) and transistor
12
being placed at the source side (MSS) of the memory transistors
10
. Except for memory transistors MC
0
and MC
15
, the drain and source of adjacent memory cells are connected together. The source of memory transistor MC
0
is connected to the drain of the next memory cell down, memory transistor MC
1
. Also, the drain of memory transistor MC
0
is connected to the source of memory transistor MSD and the drain of memory transistor MSD is connected to the metal bit line (BL). The drain of memory transistor MC
15
is connected to the source of the next memory cell above, memory transistor MC
14
. Also, the source of memory transistor MC
15
is connected to the drain of select transistor MSS and the source of select transistor MSS is connected to the common reference line (CSL), which is typically a diffusion.
It should be noted that the NAND stack unit can be replicated in both the BL direction (column) and orthogonal to the BL direction (row) to form NAND stack arrays of various sizes. NAND stack units in a column connect to a single BL while gates of memory cells within a stack connect to word lines (WL). The gates of the two select transistors connect to select lines (SSL and GSL). The WL's SSL and GSL run orthogonal to the BLs and are typically formed of polysilicon or a multilayer composite, generally including a silicide on polysilicon. The first memory cells MC
0
's) in NAND stack units along the same row are connected to WL
0
and the last memory cells (MC
15
's) in NAND stack units along the same row are connected to WL
15
. This is also true for the other memory cells and the select devices in NAND stack units along the same row.
During reading of the selected memory cell, a current path must be maintained from the selected memory cell to the CSL and BL connections of the NAND stack. Each of the fifteen non-selected NAND cells in the selected NAND stack are rendered conductive by applying sufficient gate to source voltage to not only overcome the positive enhancement threshold voltage but also to provide for a high level of conductance. Then with the gate of the selected memory cell and the CSL of the NAND stack set to ground, the state of the selected cell can be determined by sensing current flow through the selected NAND stack. When the selected memory cell has a negative depletion threshold, current will flow through the NAND stack, and when the selected memory cell has a positive enhancement threshold, little or no current will flow through the NAND stack.
Examples of read, erase and program operation bias schemes are shown in
FIG. 3
, according to conventional NAND approaches. These biases are applied during a time in which the operation achieves the desired result. A c
Hirose Ryan T.
Lancaster Loren T.
Cypress Semiconductor Corporation
Loke Steven
Sako Bradley T
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