Semiconductor nanowire with built-in stress

Details Semiconductor nanowire with built-in stress Semiconductor nanowire with built-in stress

2011-03-08

2011-03-08

Nguyen, Kimberly D (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

C257S012000, C257S018000, C257SE51040, C438S020000, C977S762000, C977S938000

Reexamination Certificate

active

07902541

ABSTRACT:
A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

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