Semiconductor multi-chip package and fabrication method

Details Semiconductor multi-chip package and fabrication method Semiconductor multi-chip package and fabrication method

2007-11-20

2007-11-20

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257SE23085

Reexamination Certificate

active

10787679

ABSTRACT:
A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.

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English language abstract of Korean Publication No. 1997-0013138.
English language abstract of Korean Publication No. 2002-0077650.

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