Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-12-28
2001-01-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
Reexamination Certificate
active
06181623
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a semiconductor MOS/BIPOLAR composite transistor operating at a high speed and a semiconductor memory device using the same.
DESCRIPTION OF THE PRIOR ART
FIG. 1
shows a circuit diagram of a conventional voltage-sensing amplifier.
FIG. 2
is a waveform showing an operation characteristic of a conventional voltage-sensing amplifier. As is well known to those skilled in the art, the voltage-sensing amplifier senses a small voltage difference between bit line BL and bit line bar /BL and converts the difference into a full-swing digital signal. As shown in
FIG. 1
, the conventional voltage-sensing amplifier includes PMOS (P-type metal oxide semiconductor) transistors P
0
and P
1
and N-type MOS (metal oxide semiconductor) transistors N
0
and N
1
. As can be seen, the voltage-sensing amplifier is incorporated with latch circuits having a positive feedback configuration using CMOS (complementary metal oxide semiconductor) inverters.
An operation of the voltage-sensing amplifier will be described with reference to
FIGS. 1 and 2
.
First, a precharge signal PRE is set to a high level and the N-type MOS transistor N
2
is turned on, resulting in equalizing a first output VO+ and a second output VO− to a predetermined level. The predetermined level is determined by device parameters of the PMOS transistors P
0
and P
1
and NMOS transistors N
0
and N
1
such as a channel length, a channel width and the like, and is typically about half the supply potential (0.5 Vdd). Next, a level of a word line rises up to a predetermined level corresponding to a sum of a supply potential (Vdd) and a threshold voltage (Vt) and a cell transistor is selectively turned on, so that a corresponding memory cell is accessed. Then, a voltage signal corresponding to data of the selected memory cell is transferred to a bit line BL and a bit line bar /BL from the selected memory cell. At the same time, the precharge signal PRE is set to a low level and the sense amplifier starts to operate. Here, the power potential (Vdd) is applied to one terminal denoted by PLAT which is coupled to the PMOS transistors P
0
and P
1
. A ground potential is applied to the other terminal denoted by NLAT which is coupled to the N-type MOS transistors N
0
and N
1
.
Referring to
FIG. 2
showing a waveform of respective signals when a high level data is sensed, a voltage signal of a sense amplifier is developed according to the data on the bit line BL and a bit line bar /BL, and then, the first output VO+ and the second output VO− are changing. As can be seen, a time delay of about 3.2 ns after the precharge signal PRE is set to a low level, the first output VO+ and the second output VO− are fully developed. Due to such a time delay, the operation speed of the memory device may be slow. That is, since the voltage-sensing amplifier depends on a capacitive load existing on the bit line BL and the bit line bar /BL, the time delay occurs until a line capacitor corresponding to the capacitive load are fully charged, wherein the line capacitor depends on an RC time constant. Therefore, there has been a problem that the sense amplifier operates slowly.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor MOS/BIPOLAR composite transistor operating at a high speed and a semiconductor memory device using the same.
In accordance with an embodiment of the present invention, there is provided a MOS/BIPOLAR composite transistor having a horizontal parasitic bipolar junction transistor connected in parallel to a MOS transistor, comprising: a semiconductor substrate of a first conductivity type; two active regions of a second conductivity type formed in the semiconductor substrate, wherein the two active regions are space from each other at a predetermined interval; a gate insulating layer formed on the semiconductor substrate between the two active regions; and a gate electrode formed on the gate insulating layer, wherein the gate electrode is electrically connected to the semiconductor substrate, whereby a channel of the first conductivity type is formed between the two active regions beneath the gate insulating layer to form a MOS transistor and simultaneously, the horizontal parasitic bipolar junction transistor is formed by the semiconductor substrate of the first conductivity type and the two active regions of the second conductivity type.
In accordance with another embodiment of the present invention, there is provided a semiconductor memory device including a memory cell array with a plurality of memory cells and a sense amplifier which detects and amplifies a data signal from the memory cell array to output a full swing signal, the sense amplifier comprising: a bit line and a bit line bar coupled to the memory cell; a data line and an inverting data lines for transferring an output of the sense amplifier; a first P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to a first level potential, a gate/base coupled to the inverting data line and a drain/collector coupled to the data line; a second P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to the first level potential, a gate/base coupled to the data line and a drain/collector coupled to the inverting data line; a first N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the data line and a gate/base coupled to the inverting data line; a second N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the inverting data line and a gate/base coupled to the data line; a first load coupled between a source/emitter of the first N-type MOS/BIPOLAR composite transistor and a second level potential; and a second load coupled between a source/emitter of the second N-type MOS/BIPOLAR composite transistor and the second level potential.
In accordance with further another embodiment of the present invention, there is provided a semiconductor memory device including a memory cell array with a plurality of memory cells and a sense amplifier which detects and amplifies a data signal from the memory cell array to output a full swing signal, the sense amplifier comprising: a bit line and a bit line bar coupled to the memory cell; a data line and an inverting data line to which input/output data are applied; a first P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to a first level potential, a gate/base coupled to a second output node and a drain/collector coupled to a first output node; a second P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to the first level potential, a gate/base coupled to the first output node and a drain/collector coupled to the second output node; a first N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the first output node and a gate/base coupled to the second output node; a second N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the second output node and a gate/base coupled to the first output node; a first load coupled between a source/emitter of the first N-type MOS/BIPOLAR composite transistor and a second level potential; a second load coupled between a source/emitter of the second N-type MOS/BIPOLAR composite transistor and the second level potential; a first select MOS/BIPOLAR composite transistor coupled between the bit line and a source/emitter of the first N-type MOS/BIPOLAR composite transistor, wherein the first select transistor is turned on in response to a sense enable signal; a second select MOS/BIPOLAR composite transistor coupled between the bit line bar and the source/emitter of the second N-TYPE MOS/BIPOLAR composite transistor, wherein the second select transistor is turned on in response to the sense enable signal; a first column-select MOS/BIPOLAR composite transistor coupled between the first output node and the data line; and a second column-select transistor coupled between
Gang Yung-Jin
Shim Young-Bo
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Phan Trong
LandOfFree
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