Metal fusion bonding – Process – With protecting of work or filler or applying flux
Reexamination Certificate
2001-01-26
2002-12-17
Elve, M. Alexandra (Department: 1725)
Metal fusion bonding
Process
With protecting of work or filler or applying flux
C228S218000
Reexamination Certificate
active
06494361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic component packaging and more particularly to a method of fabricating a substrate for a module package.
2. Description of Related Art
A high density build-up laminate substrate was commonly used as an interposer for a high pin-count flip chip integrated circuit package. In this flip chip integrated circuit package, the die pads of the integrated circuit chip were bumped with solder bumps. The integrated circuit chip was then placed on the substrate such that the solder bumps were placed in contact with solderable flip chip bond pads of the substrate. The assembly was then heated to reflow the solder bumps and thus form the electrical connections between the die pads of the die and the flip chip bond pads of the substrate in a well-known manner.
Two types of bond pads of the substrate were commonly used. With a non-solder mask defined (NSMD) bond pad, the wettable area of a bond pad of the substrate was defined by the edge of the metallic trace which formed the bond pad, i.e., the bond pad itself defined the wettable area. However, use of the NSMD bond pad resulted in cracking of the dielectric buildup layer. Consequently, the reliability and assembly yield of the flip chip integrated circuit package was undesirably reduced.
Alternatively, with a solder mask defined (SMD) bond pad, the wettable area of a bond pad of the substrate was defined by the solder mask, i.e., a portion of the metallization which formed the bond pad was exposed through the solder mask, and this portion of the metallization defined the wettable area of the SMD bond pad.
However, use of the SMD bond pad as a flip chip SMD bond pad greatly reduced the collapse of the solder bump on the die pad of the integrated circuit chip during flip chip attachment of the integrated circuit chip to the substrate. Disadvantageously, this increased the probability of an open solder joint connection between a die pad of the integrated circuit chip and a flip chip SMD bond pad of the substrate resulting in an undesirable assembly yield loss. To decrease this probability of an open solder joint connection, a controlled amount of solder was applied to the flip chip SMD bond pad of the substrate. This solder on the flip chip SMD bond pad was commonly referred to as a solder-on-pad (SOP).
FIG. 1
is a cross-sectional view of a flip chip ball grid array substrate
10
in accordance with the prior art. Substrate
10
included a central dielectric layer
12
, an upper dielectric layer
14
, and a lower dielectric layer
16
. Upper dielectric layer
14
and lower dielectric layer
16
were commonly referred to as dielectric buildup layers.
Formed on upper dielectric layer
14
were metallizations
18
, sometimes called traces. An upper solder mask
20
was patterned to expose portions of metallizations
18
to form flip chip SMD bond pads. Solder-on-pads
22
, i.e., solder, were formed on these flip chip SMD bond pads.
Formed on lower dielectric layer
16
were metallizations
24
, sometimes called traces. A lower solder mask
26
was patterned to expose portions of metallizations
24
to form ball grid array (BGA) SMD bond pads
28
. BGA solder balls (not shown) were formed on BGA SMD bond pads
28
. To allow BGA solder balls to be formed on BGA SMD bond pads
28
, it was important that BGA SMD bond pads
28
were wettable with solder.
There were several surface finishes that were used to insure that BGA SMD bond pads
28
were wettable. Among these were electrolytic Ni/Au plating, electroless Ni/Au plating, full body gold, and copper with a coating of organic solderability protectant (OSP).
With electrolytic Ni/Au plating, it was often difficult to provide bus bars required for the electroplating thus making electrolytic Ni/Au plating impractical for many applications. On the other hand, electroless Ni/Au plating resulted in the formation of a brittle intermetallic between the BGA solder ball and the electroless Ni/Au plating, which undesirably caused failure in the BGA solder joint.
With full body gold, metallizations
18
,
24
were entirely covered with a layer of gold. Solder masks
20
,
26
were formed on this layer of gold. However, since solder masks
20
,
26
had poor adhesion to gold as compared to copper, failures due to the delamination of solder masks
20
,
26
occurred.
For the above reasons, metallizations
24
formed of copper and coated with organic solderability protectant formed the optimum surface finish for BGA SMD bond pads
28
. However, there were inherent difficulties in applying the organic solderability protectant to metallizations
24
.
Solder-on-pads
22
were initially formed on metallizations
18
. A tape material
30
was applied to cover and protect solder-on-pads
22
. Substrate
10
was then subjected to an OSP etch process as indicated by the arrows
32
. This OSP etch process was necessary to remove oxidation and impurities on BGA SMD bond pads
28
. Tape material
30
prevented the chemical etchant from attacking solder-on-pads
22
. The organic solderability protectant was then applied to BGA SMD bond pads
28
.
Tape material
30
was then removed. Undesirably, tape material
30
left a residue on solder-on-pads
22
which increased the probability of open solder joint formation during flip chip attachment of the integrated circuit chip to substrate
10
and thus reduced assembly yield. Further, use of tape material
30
was relatively complex, labor-intensive, and thus expensive.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a method of forming a substrate includes an organic solderability protectant (OSP) etch operation to prepare solder mask defined (SMD) bond pads on an upper surface and a lower surface of a dielectric substrate layer for subsequent OSP application. In an OSP application operation, organic solderability protectant is applied to all of the solder mask defined bond pads, e.g., to flip chip SMD bond pads, to ball grid array (BGA) SMD bond pads and to surface mounted device SMD bond pads.
In a solder paste application operation, solder paste is applied on the flip chip SMD bond pads. In a solder paste reflow operation, the solder paste is reflowed to form solder-on-pads (SOPs) on the flip chip SMD bond pads. This reflow is performed in an inert atmosphere, e.g., in an oxygen deficient atmosphere, to inhibit oxidation of the organic solderability protectant on the remaining SMD bond pads, e.g., on the BGA SMD bond pads and the surface mounted device SMD bond pads, and also to inhibit oxidation of the remaining SMD bond pads themselves.
Recall that in the prior art, the solder-on-pads were formed prior to application of the organic solderability protectant on the BGA SMD bond pads. The organic solderability protectant had to be applied after the solder-on-pads were formed because otherwise the organic solderability protectant would have degraded during the formation of the solder-on-pads thus unacceptably exposing and subjecting to oxidation the BGA SMD bond pads. Disadvantageously, tape material had to be utilized to protect the solder-on pads during the OSP etching and application processes. However, use of the tape material to protect the solder-on-pads was relatively complex, labor-intensive, and expensive.
In stark contrast, the solder-on-pads are formed after the OSP etch operation and the OSP application operation in accordance with the present invention. Accordingly, use of the tape material of the prior art and the associated complexity and cost to protect the solder-on-pads is avoided.
In accordance with one embodiment of the present invention, during a flux residue removal operation, flux residue generated during the reflow of the solder paste to form the solder-on-pads is removed. The flux residue is removed using water. Advantageously, by using water, degradation of the organic solderability protectant of the remaining SMD bond pads, e.g., on the BGA SMD bond pads and the surface mounted device SMD bond pads, is inhibi
Aday Jon G.
Scanlan Christopher
Amkor Technology Inc.
Elve M. Alexandra
Gunnison McKay & Hodgson, L.L.P.
Hodgson Serge J.
Tran Len
LandOfFree
Semiconductor module package substrate fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor module package substrate fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor module package substrate fabrication method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2941568