Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-08-30
2004-09-28
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S777000, C257S723000, C257S692000
Reexamination Certificate
active
06798056
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor module such as a memory module. A “semiconductor module” herein refers to a module having one or more parts including a semiconductor package mounted on one substrate.
2. Description of the Background Art
Information equipment such as a personal computer has a memory module mounted as a semiconductor module. A common and conventional memory module will now be described. First, in
FIG. 9
, a semiconductor package
1
mounted on a memory module is shown. Semiconductor package
1
includes a package body
2
and a plurality of leads
3
protruding in parallel, respectively from opposing side portions. A dimension of semiconductor package
1
is determined by an organization for standardizing a semiconductor package, JEDEC (Joint Electron Device Engineering Council), and a “TSOP” (Thin Small Out-line Package) of “400 mil” is one example. When semiconductor package
1
is an SDRAM (Synchronous Dynamic Random Access Memory), 54 pins are provided, pitch A between leads
3
is set to 0.8 mm, and width B per one lead
3
is set to 0.3 mm.
As shown in
FIG. 10
, a memory module
100
has semiconductor package
1
mounted on a surface of substrate
4
in a prescribed arrangement. On the surface of substrate
4
, in addition to semiconductor package
1
, a packaged parts
5
a
,
5
b
such as a resistance, and a buffer IC (Integrated Circuit)
6
for amplifying and timing a signal of the memory are also mounted. In order to make effective use of a limited area on substrate
4
, packages are often mounted on opposing surfaces of substrate
4
, as shown in FIG.
11
. On both surfaces of substrate
4
, pads
7
are formed in positions corresponding respectively to leads
3
, which are electrically connected to pads
7
respectively. In an example shown in
FIGS. 10 and 11
, nine semiconductor packages
1
are mounted on one surface of substrate
4
of 133.35 mm long and 31.75 mm wide, which is a dimension determined in accordance with JEDEC standard. This means that, in total, eighteen semiconductor packages
1
are mounted on both surfaces.
As personal computers and the like are more sophisticated, an increase of memory capacity has been demanded. Accordingly, more semiconductor packages need to be mounted per one substrate. In an effort to achieve this, in Japanese Patent Laying-Open No. 4-276649, a technique to stack and mount a semiconductor package is proposed. According to the technique, as shown in
FIG. 12
, a semiconductor package
1
e
having a longer lead is prepared in addition to semiconductor package
1
. As shown in
FIGS. 13 and 14
, a two-layered structure is provided on one surface of substrate
4
. That is, an inner pad
7
having a conventional arrangement and a pad
7
e
arranged outside the former together form pads on the surface of substrate
4
. In the two-layered structure of the semiconductor packages, lead
3
of semiconductor package
1
located on a side close to substrate
4
(hereinafter, referred to as a “lower layer”) is connected to pad
7
, while a lead
3
e
of semiconductor package
1
e
overlying the former on a side far from substrate
4
(hereinafter, referred to as an “upper layer”) relative to semiconductor package
1
is connected to pad
7
e
, going around the outside of lead
3
. In this case, however, a row of pad
7
e
for upper layer semiconductor package
1
e should be arranged parallel to, and outside, a row of pad
7
for lower layer semiconductor package
1
. Therefore, width of the area occupied on substrate
4
will be larger. Consequently, for example, though nine semiconductor packages could conventionally be arranged per one layer on one surface of substrate
4
, only eight semiconductor packages per one layer on one surface can be arranged, as can be seen in a memory module
101
shown in FIG.
15
.
Further improved techniques are possible as described below. As shown in
FIG. 16
, a semiconductor package if is prepared, which is a 400 mil package having 54 pins in accordance with a conventional standard. Though pitch between leads
3
f
is the same as a conventional example, width C per one lead
3
f
is made smaller to 0.16 mm. This semiconductor package
1
f
is provided as a lower layer. Separately, a semiconductor package
1
g
is prepared having a lead
3
g
that has the same length as lead
3
f
when viewed from the top and has longer length than the same when viewed from the side. This package is provided as an upper layer. Width C per one lead
3
g
of semiconductor package
1
g
is also made smaller to 0.16 mm. Both packages are mounted, with one overlying the other, as shown in
FIGS. 17 and 18
. The pad of upper layer semiconductor package
1
g
and the pad of lower layer semiconductor package
1
f
are alternately arranged, and lead
3
g
of semiconductor package
1
g
is interposed between leads
3
f
of semiconductor package
1
f
respectively. Consequently, as can be seen in a memory module
102
shown in
FIG. 19
, nine packages can be arranged per one layer on one surface of substrate
4
, as in a conventional example.
In
FIG. 20
, an enlarged view of the vicinity of a root portion of the lead is shown. Generally, a plurality of leads protruding in parallel from a side portion of a package body of the semiconductor package are manufactured in the following manner. A package body
2
portion is formed with resin mold so as to partially cover a leadframe
14
integrally formed. Thereafter, as shown in
FIG. 21
, a punch region
13
set on a dambar
12
linking each lead in a portion protruding from the side portion of package body
2
is punched through, and thus each lead is separated. In an attempt to punch the region to completely remove dambar
12
linking each lead, a puncher may strike a lead portion and damage the lead, or useful life of the puncher may be shortened. Therefore, usually, punch region
13
is set to a size covering only a main portion of dambar
12
with a small clearance from the lead portion, not exactly covering both full ends of dambar
12
. Accordingly, as shown in
FIG. 22
, after punching, a dambar residual portion
8
will remain in the middle of lead
3
. Lead
3
is folded thereafter, to have a shape shown in FIG.
23
. In
FIG. 23
, the semiconductor package is shown, disposed on substrate
4
. Here, the lead can be divided in three parts: a lead drawn-out portion
31
horizontally drawn from the side portion of package body
2
; a lead extending-downward portion
32
hereinafter, referred to as a “lead downward portion”) extending down to the surface of substrate
4
; and a lead foot portion
33
for contacting pad electrode
7
.
A side view of the techniques described with reference to
FIGS. 16
to
19
is shown in FIG.
24
. Width of the lead is made smaller in both upper and lower layers so that lead
3
g
of upper layer semiconductor package
1
g
passes a gap between leads
3
f
of lower layer semiconductor package
1
f
. In practice, however, as dambar residual portion
8
is present, the gap where lead
3
g
can pass is narrow. Therefore, only a slight displacement of a position of either the upper or lower semiconductor package may cause a contact of lead
3
f
with lead
3
g.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor module capable of increasing the mountable number of semiconductor packages per one layer on one surface of a substrate as well as avoiding contacts between leads due to a dambar residual portion.
In order to achieve the object above, a semiconductor module according to the present invention includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the lower layer semiconductor package. The lower layer semiconductor package and the upper layer semiconductor package include a package body and a plurality of leads protruding in paralle
Kasatani Yasushi
Matsuura Tetsuya
Michii Kazunari
Nguyen Dilinh
Pham Long
Renesas Technology Corp.
LandOfFree
Semiconductor module having an upper layer semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor module having an upper layer semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor module having an upper layer semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3248295