Semiconductor method having silicon-diffused metal wiring layer

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S774000, C257SE23145, C257SE21593

Reexamination Certificate

active

07737555

ABSTRACT:
In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

REFERENCES:
patent: 5242858 (1993-09-01), Sakamoto et al.
patent: 5310626 (1994-05-01), Fernandes et al.
patent: 5565708 (1996-10-01), Ohsaki et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6090699 (2000-07-01), Aoyama et al.
patent: 6207552 (2001-03-01), Wang et al.
patent: 6251775 (2001-06-01), Armbrust et al.
patent: 6518184 (2003-02-01), Chambers et al.
patent: 6627554 (2003-09-01), Komada
patent: 6737728 (2004-05-01), Block et al.
patent: 6762500 (2004-07-01), Ahn et al.
patent: 6787480 (2004-09-01), Aoki et al.
patent: 6794286 (2004-09-01), Aoyama et al.
patent: 6979846 (2005-12-01), Yagishita et al.
patent: 7132732 (2006-11-01), Ohto et al.
patent: 7229921 (2007-06-01), Hironaga et al.
patent: 7232757 (2007-06-01), Noguchi et al.
patent: 2002/0009855 (2002-01-01), Kim
patent: 2002/0024142 (2002-02-01), Sekiguchi
patent: 2002/0052106 (2002-05-01), Ikura
patent: 2002/0093097 (2002-07-01), Kamoshima et al.
patent: 2002/0140101 (2002-10-01), Yang et al.
patent: 2002/0155702 (2002-10-01), Aoki et al.
patent: 2002/0163083 (2002-11-01), Hatano et al.
patent: 2002/0192937 (2002-12-01), Ting et al.
patent: 2003/0068582 (2003-04-01), Komada et al.
patent: 2003/0073301 (2003-04-01), Nguyen et al.
patent: 2003/0111730 (2003-06-01), Takeda et al.
patent: 2003/0137050 (2003-07-01), Chambers et al.
patent: 2003/0173671 (2003-09-01), Hironaga et al.
patent: 2004/0004288 (2004-01-01), Sekiguchi
patent: 2004/0147117 (2004-07-01), Ngo et al.
patent: 2004/0150113 (2004-08-01), Tonegawa
patent: 2004/0188748 (2004-09-01), Matsuhashi
patent: 2004/0190220 (2004-09-01), Matsuhashi
patent: 2004/0266171 (2004-12-01), Aoki et al.
patent: 2005/0023697 (2005-02-01), Ahn et al.
patent: 2006/0289993 (2006-12-01), Ahn et al.
patent: 03-262125 (1991-11-01), None
patent: 06-177128 (1994-06-01), None
patent: 11-186273 (1999-07-01), None
patent: 11-204523 (1999-07-01), None
patent: 2000-058544 (2000-02-01), None
patent: 2000-150517 (2000-05-01), None
patent: 2000-349085 (2000-12-01), None
patent: 2001-291720 (2001-10-01), None
patent: 2003-347299 (2003-12-01), None
patent: 1998-084723 (1998-01-01), None
patent: 1999-005857 (1999-01-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor method having silicon-diffused metal wiring layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor method having silicon-diffused metal wiring layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor method having silicon-diffused metal wiring layer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4244093

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.