Semiconductor metal interconnect reliability test structure

Details Semiconductor metal interconnect reliability test structure Semiconductor metal interconnect reliability test structure

2000-10-24

2003-05-27

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S773000, C257S774000

Reexamination Certificate

active

06570181

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention is related in general to the field of semiconductor processing and testing, and more particularly, to a semiconductor metal interconnect reliability test structure.
BACKGROUND OF THE INVENTION
In sub-half micron metalization systems, reliability-limiting wear out mechanisms include electromigration and stress-induced voiding. To test the reliability of any metalization process, an electromigration and stress void test is conducted on a test structure fabricated with the same processes and technology as the device in question. These tests typically involve subjecting the test structure to high temperature and/or high voltage and current conditions.
Conventional test structures suffer from several disadvantages and do not provide ideal test results for post-testing study and analysis.
SUMMARY OF THE INVENTION
It has been recognized that it is desirable to provide a metal interconnect reliability test structure that enables proper testing of electromigration and stress voiding.
In one aspect of the invention, a semiconductor reliability test structure is formed on a face of a semiconductor substrate. The test structure includes a chain of a plurality of long test links formed of a first semiconductor material, where the plurality of long test links are alternately interconnected by a plurality of short connecting links formed of a second semiconductor material. The test structure further includes first and second bond pads coupled to the first and second ends of the chain, respectively.
In another aspect of the invention, a semiconductor metal interconnect reliability test structure is formed on a face of a semiconductor substrate. The test structure includes a chain formed of a plurality of long test links formed in a first metal layer. The plurality of long test links are alternately interconnected by a plurality of short connecting links formed in a second metal layer. The test structure further includes first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively. A plurality of vias connect the first and second metal layers of the long test links and the short connecting links. The plurality of the long test links are generally aligned along a first axis and the plurality of short connecting links are generally aligned along a second axis, the alternating long and short connecting links generally forming a serpentine configuration.
In yet another aspect of the present invention, a semiconductor metal interconnect reliability test structure is formed on a face of a semiconductor substrate. The test structure includes a chain formed of a plurality of long test links formed in a first metal layer. The plurality of long test links are alternately interconnected by a plurality of short connecting links formed in a second metal layer. The test structure further includes first and second bond pads formed in the second metal layer and coupled to the first and second ends of the chain, respectively. A plurality of vias connect the first and second metal layers of the long test links and the short connecting links. The plurality of the long test links are generally aligned along a first axis and the plurality of short connecting links are generally aligned along a second axis, the alternating long and short connecting links generally forming a serpentine configuration. At least one intermediate bond pad is coupled to a short connecting link. A plurality of tick marks are formed on the face of the semiconductor substrate thereby providing a location reference for positions in the plurality of long test links.


REFERENCES:
patent: 5952674 (1999-09-01), Edelstein et al.
patent: 6297644 (2001-10-01), Jarvis et al.

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