Semiconductor memory with vertical charge-trapping memory...

Details Semiconductor memory with vertical charge-trapping memory... Semiconductor memory with vertical charge-trapping memory...

2006-01-31

2006-01-31

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S074000, C257S296000, C257S329000, C257S330000, C438S239000, C438S212000, C438S259000, C438S270000

Reexamination Certificate

active

06992348

ABSTRACT:
Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

REFERENCES:
patent: 5763310 (1998-06-01), Gardner
patent: 5966603 (1999-10-01), Eitan
patent: 6239465 (2001-05-01), Nakagawa
patent: 6486028 (2002-11-01), Chang et al.
patent: 6583479 (2003-06-01), Fastow et al.
patent: 6881994 (2005-04-01), Lee et al.
patent: 2002/0024092 (2002-02-01), Palm et al.
patent: 100 39 441 (2002-02-01), None
patent: 0 967 654 (1999-12-01), None

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