Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-25
2004-09-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S304000, C257S309000, C438S243000, C438S244000, C438S246000
Reexamination Certificate
active
06787837
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-193519, filed Jun. 26, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device using an SOI (Silicon On Insulator) substrate and a method of manufacturing the same and, more particularly, to the structure of a trench capacitor.
2. Description of the Related Art
The integration degree of a semiconductor integrated circuit has been improved year by year, and in particular, the integration degree of a memory circuit makes remarkable progress. For example, since a DRAM (Dynamic Random Access Memory) cell comprised of one transistor and one capacitor is required for an increase in integration degree and a decrease in manufacturing cost, an area occupied by components needs to be reduced. However, when the area and width of a resistive element need to be made smaller along with DRAM cell downsizing, it is difficult to maintain the electrical characteristics. To solve this, a trench capacitor capable of reducing the occupied area and maintaining the electrical characteristics is proposed.
FIGS. 32
to
38
are sectional views showing the steps in manufacturing a semiconductor memory device having a trench capacitor according to the prior art. A method of manufacturing the semiconductor memory device according to the prior art will be briefly described below.
As shown in
FIG. 32
, an SOI (Silicon On Insulator) substrate
111
is formed first. The SOI substrate
111
is formed from first and second semiconductor layers
111
a
and
111
b
and a buried layer
111
c
which is made of, e.g., an SiO
2
film and formed between the first and second semiconductor layers
111
a
and
111
b
. An SiO
2
film
112
is formed on the SOI substrate
111
, and an SiN film
113
is formed on the SiO
2
film
112
. A trench
117
is then formed to reach the first semiconductor layer
111
a
through the SiN film
113
, SiO
2
film
112
, second semiconductor layer
111
b
, and buried layer
111
c.
An AsSG (Arsenic Silicate Glass) film
118
is formed on the inner side and bottom surfaces of the trench
117
and on the SiN film
113
. The portion of the AsSG film
118
is removed by isotropic etching using a hydrofluoric acid solution. As in the AsSG film
118
is diffused into the first semiconductor layer
111
a
at the outer side surface of the trench
117
by high-temperature annealing. With this process, a plate diffusion layer
121
a
serving as a capacitor electrode is formed in the first semiconductor layer
111
a
along the side and bottom surfaces of the trench
117
. The AsSG film
118
is then removed.
As shown in
FIG. 33
, a capacitor insulating layer
122
is formed on the inner side and bottom surfaces of the trench
117
and on the SiN film
113
, and a polysilicon film
123
with As serving as a prospective capacitor electrode is formed on the capacitor insulating film
122
. The polysilicon film
123
and capacitor insulating film
122
are removed so as to leave them inside the trench
117
in the first semiconductor layer
111
a
. With this process, a trench capacitor
127
formed from the plate diffusion layer
121
a
, capacitor insulating layer
122
, and polysilicon film
123
is formed in the trench
117
in the first semiconductor layer
111
a
. A TEOS film
124
is then formed on the polysilicon film
123
and the side surface of the trench
117
at the second semiconductor layer
111
b
and buried layer
111
c.
As shown in
FIG. 34
, a polysilicon film
126
containing As is formed in the trench
117
and on the SiN film
113
.
As shown in
FIG. 35
, the polysilicon film
126
is removed by anisotropic etching such that its upper surface has a lower level than that of the second semiconductor layer
111
b.
As shown in
FIG. 36
, the TEOS film
124
is removed by anisotropic etching such that its upper surface has lower level than that of the polysilicon film
126
.
As shown in
FIG. 37
, a polysilicon film
140
containing As is formed in the trench
117
and on the SiN film
113
.
As shown in
FIG. 38
, the polysilicon film
140
is removed by anisotropic etching such that its upper surface has a lower level than that of the second semiconductor layer
111
b.
In this fashion, a transistor connection portion
128
formed from the polysilicon films
126
and
140
is formed and electrically connected to the trench capacitor
127
.
In the prior art described above, when the AsSG film
118
is removed by isotropic etching using a hydrofluoric acid solution, the buried layer
111
c
and SiO
2
film
112
retreat in the lateral direction, thus undesirably forming recessed portions
130
a
and
130
b
, as shown in FIG.
32
. With this structure, when the trench
117
is filled with the polysilicon film
126
, a gap
141
is generated in the region in the trench
117
in which the recessed portion
130
a
is present, as shown in FIG.
34
.
This causes a decrease in sectional area of the connection portion
128
serving as the current path between the capacitor
127
and a transistor (not shown). Therefore, since a parasitic resistance as the DRAM cell increases, the memory cannot realize high-speed read/write of an electrical signal as a DRAM element.
BRIEF SUMMARY OF THE INVENTION
A semiconductor memory device according to a first aspect of the present invention comprises a first semiconductor layer, a buried insulating layer formed on the first semiconductor layer, a second semiconductor layer formed on the buried insulating layer, a trench formed to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, the trench comprising a retreated portion at which a side surface of the buried insulating layer retreats with respect to a side surface of the second semiconductor layer, and the trench defining a first opening width at the second semiconductor layer, a first capacitor electrode formed in the first semiconductor layer along a side surface and a bottom surface of the trench, a capacitor insulating film formed in the trench to cover the first capacitor electrode, a second capacitor electrode formed in the trench in the first semiconductor layer to oppose the first capacitor electrode through the capacitor insulating film, an insulating film formed on a side surface of the retreated portion, the insulating film defining a second opening width and a third opening width, the second opening width serving as a width at the buried insulating layer, the second opening width being not more than the first opening width, and the third opening width serving as a width at a boundary portion between the buried insulating layer and first semiconductor layer, and a connection portion which is formed in the trench in the buried insulating layer and the second semiconductor layer and electrically connected to the second capacitor electrode.
A semiconductor memory device according to a second aspect of the present invention comprises a first semiconductor layer, a buried insulating layer formed on the first semiconductor layer, a second semiconductor layer formed on the buried insulating layer, a trench formed to reach the first semiconductor layer through the second semiconductor layer and the buried insulating layer, an insulating film formed on a side surface of the trench at a level lower than an upper surface of the second semiconductor layer, a first capacitor electrode formed on the insulating film and a bottom surface of the trench, a capacitor insulating film formed in the trench to cover the first capacitor electrode, a second capacitor electrode formed in the trench to oppose the first capacitor electrode through the capacitor insulating film, and a connection portion which is formed in the trench in the second semiconductor layer and electrically connected to the second capacitor electrode.
A method of manufacturing a semiconductor memory devic
Nelms David
Nguyen Dao H.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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