Semiconductor memory with test circuit

Details Semiconductor memory with test circuit Semiconductor memory with test circuit

1997-02-12

1997-11-04

Canney, Vincent P.

Excavating

371 251, 36518911, G06F 1100

Patent

active

056848099

ABSTRACT:
A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.

REFERENCES:
patent: 5457400 (1995-10-01), Ahmad et al.
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patent: 5487037 (1996-01-01), Lee
patent: 5528603 (1996-06-01), Canella et al.
patent: 5532963 (1996-07-01), Kushiyama et al.
Jun'ichi Inoue, et al., "Parallel Testing Technology for VLSI Memories", 1987 International Test Conference, 1987 IEEE--Paper 45.1, 1066-1071, (1987).
Shigeru Mori, et al., "A 45ns 64Mb DRAM with a Merged Match-line Test Architecture", ISSCC91/Session 6/High-Density DRAM/Paper TA 64, 1991 IEEE International Solid State Circuit Conference, 110-111, (1991).

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