Semiconductor memory with source/drain regions on walls of...

Details Semiconductor memory with source/drain regions on walls of... Semiconductor memory with source/drain regions on walls of...

2000-12-11

2004-04-20

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S315000, C257S318000, C257S330000

Reexamination Certificate

active

06724035

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a semiconductor memory device and a semiconductor memory device, and more specifically, it relates to a process for producing a semiconductor memory device and a semiconductor memory device that have a floating gate and a control gate with an asymmetric source/drain region.
2. Description of the Related Art
A process for producing a semiconductor memory device having an asymmetric source/drain region is proposed, for example, in Japanese Patent Application Laid-open HEI 4(1992)-137558.
The process for producing a semiconductor memory device according thereto will be described below. FIG.
16
(
a
) to FIG.
17
(
g
) are cross sectional views on line X-X′ in FIG.
15
(
a
), and FIG.
16
(
a
) to FIG.
17
(
g
′) are cross sectional views on line Y-Y′ in FIG.
15
(
a
).
As shown in FIGS.
16
(
a
) and
16
(
a
′), on an active region of a P type semiconductor substrate
21
, a tunnel oxide film having a film thickness of about 10 nm, a phosphorous-doped polycrystalline silicon film
3
of about 100 nm and a silicon nitride film
4
of about 100 nm are sequentially deposited, and the silicon nitride film
4
, the polycrystalline silicon film
3
and the tunnel oxide film
2
are sequentially etched by a reactive ion etching using a resist R
21
(see FIG.
15
(
b
)) patterned by a photolithography technique as a mask, so as to pattern for a floating gate.
After removing the resist R
21
, as shown in FIGS.
16
(
b
) and
16
(
b
′), arsenic ions, for example, are implanted at 0° with respect to the normal line of the substrate (hereinafter referred to as “0°”) with an implantation energy from about 5 to about 40 keV and a dose from about 5×10
12
to about 5×10
13
ions/cm
2
using the floating gate as a mask, so as to form a low concentration impurity layer
25
.
Thereafter, as shown in FIGS.
16
(
c
) and
16
(
c
′), after covering the low concentration impurity layer
25
with a resist R
24
by a photolithography technique, arsenic ions are implanted at 0°, with an implantation energy from about 5 to about 40 keV and a dose from 1×10
15
to 1×10
16
ions/cm
2
, so as to form a high concentration impurity layer
26
.
After removing the resist R
24
, as shown in FIGS.
16
(
d
) and
16
(
d
′), a silicon oxide film to be an insulating film is deposited by a CVD (chemical vapor deposition) method to about 150 nm, and is etched back by a reactive ion etching, so as to form a side wall spacer
28
on a side wall of the floating gate. At this time, the width of the side wall spacer
28
is determined in such a manner that the high concentration impurity layer
26
is not present immediately under the side wall spacer
28
on the side of the low concentration impurity layer
25
.
Subsequently, as shown in FIGS.
16
(
e
) and
16
(
e
′), arsenic ions, for example, are implanted at 0°, with an implantation energy from about 5 to about 40 keV and a dose from 1×10
15
to 1×10
16
ions/cm
2
using the side wall spacer
28
as a mask, so as to form a high concentration impurity layer
29
.
Thereafter, the impurities are activated by a thermal treatment. A silicon oxide film to be a dielectric film is deposited by a CVD method to a thickness from about 400 nm to about 600 nm and is subjected to a CMP (chemical mechanical polishing) method, so as to fill a silicon oxide film
30
in a space between the floating gates. The silicon nitride film
24
is then removed by hot phosphoric acid. Subsequently, as shown in FIGS.
17
(
f
) and
17
(
f
′), a phosphorous-doped polycrystalline silicon film
31
is deposited in a thickness of about 100 nm to increase the gate coupling ratio.
Thereafter, as shown in FIGS.
17
(
g
) and
17
(
g
′), the polycrystalline silicon film
31
is processed by a reactive ion etching using a resist R
22
patterned by a photolithography technique (see FIG.
15
(
b
)), so as to form a stacked floating gate on the polycrystalline silicon film
23
. After removing the resist R
22
, a silicon oxide film of 6 nm is deposited by a thermal oxidation on the surface of the stacked floating gate, and a silicon nitride film of 8 nm and a silicon oxide film of 6 nm are deposited thereon by a CVD method, in this order, so as to form an ONO film
32
(silicon oxide film/silicon nitride film/silicon oxide film) to be a dielectric film between a floating gate and a control gate. A polycide film (comprising a polycrystalline silicon film doped with phosphorous ions as an impurity of 100 nm and a tungsten silicide film of 100 nm) to be a control gate material is then deposited to a thickness of about 200 nm, and the polycide film, the ONO film
32
, the polycrystalline silicon film
31
and the polycrystalline silicon film
23
are sequentially etched by a reactive ion etching using a resist R
23
patterned by a photolithography technique (see FIG.
15
(
b
)) as a mask, so as to form a control gate
33
and a floating gate
34
. After removing the resist R
23
, boron ions, for example, are implanted at 0° with an implantation energy from about 10 to about 40 keV and a dose from 5×10
12
to 5×10
13
ions/cm
2
using the control gate
33
as a mask, so as to form an impurity layer
35
for isolation of memory elements.
Thereafter, according to the known process, an interlayer dielectric film is formed, and a contact hole and metallic wiring are formed.
An equivalent circuit of the source/drain asymmetric semiconductor memory device thus formed is shown in FIG.
18
.
In
FIG. 18
, Tr.
00
to Tr.
32
are memory cells having a floating gate, WL
0
to WL
3
are word lines connected to the control gates of the memory cells, and BL
0
to BL
3
are bit lines connected to the drain/source common diffusion wiring layers of the memory cells. The word line WL
0
is connected to the control gates of Tr.
00
, Tr.
01
and Tr.
02
, and the word line WL
1
is connected to the control gates of Tr.
10
, Tr.
11
and Tr.
12
, respectively (the rest is omitted). The bit line BL
1
is connected to the drains of Tr.
01
, Tr.
11
, Tr.
21
and Tr.
31
or the sources of Tr.
00
, Tr.
10
, Tr.
20
and Tr.
30
, and the bit line BL
2
is connected to the drains of Tr.
02
, Tr.
12
, Tr.
22
and Tr.
32
or the sources of Tr.
01
, Tr.
11
, Tr.
21
and Tr.
31
.
The operation voltages of reading, writing and erasing a selected Tr.
11
in
FIG. 18
are shown in Table 1. Furthermore,
FIG. 19
shows the state of reading Tr.
11
,
FIG. 20
shows the state of writing Tr.
11
, and
FIG. 21
shows the state of erasing Tr.
10
to Tr.
12
including Tr.
11
connected to the word line WL
1
.
TABLE 1
Non-
Non-
Selected
selected
Selected
selected
WL
WL
BL
BL
SL
Substrate
WL1
WL0, 2
BL1
BL0, 3
BL2
PW
Reading
 3
0
0
open
1
0
Writing
−12  
open
4
open
open
0
Erasing
12
open
−8  
−8
−8  
−8  
It is assumed that the writing of the memory cell is defined, for example, as Vth<2 V, and the erasing thereof is defined, for example, as Vth>4 V.
The writing method will be described with reference to FIG.
19
and Table 1. When a voltage of 3 V is applied to the control gate, the substrate and the drain are grounded and a voltage of 1 V is applied to the source, the information in the memory cell can be read out by detecting whether or not an electric current i flows between the source and the drain.
The reading method will be described with reference to FIG.
20
and Table 1. Upon writing in Tr.
11
, as shown in Table 1, a voltage of −12 V is applied to the control gate, the substrate is grounded, and a voltage of 4 V is applied to the drain, whereby electrons are drawn from the floating gate by using an FN tunnel electric current flowing in a thin oxide film in the overlapping region of the drain and the floating gate. At this time, while a voltage 4 V is also applied to the source of Tr.
10
that is common to the drain applied with the

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