Semiconductor memory with sensing stability

Details Semiconductor memory with sensing stability Semiconductor memory with sensing stability

1997-05-13

1999-07-06

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

3652385, 36523006, G11C 800

Patent

active

059205199

ABSTRACT:
A memory having a read function for generating a plurality of data bits on a single output pin includes a control circuit, a sense amplifier circuit, and a decoder. The control circuit generates a decoder control pulse responding to the control pulse generated from an address transition detector receiving a first address. The sense amplifier circuit senses data bits from a memory array of the memory and is coupled to the output pin through a data output buffer. The decoder receives a second address and provides decoding signals to the sense amplifier circuitry in response to the control pulse generated from the control circuit. The read-out operation according to the invention is performed sufficiently and stably even when a propagation skew occurs between the first address and the second address.

REFERENCES:
patent: 5404327 (1995-04-01), Houston
patent: 5592426 (1997-01-01), Jallice et al.
patent: 5636177 (1997-06-01), Fu
patent: 5694370 (1997-12-01), Yoon

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