Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-03-25
2003-10-28
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S208000
Reexamination Certificate
active
06639862
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a semiconductor memory in which memory cells are refreshed again through an amplifier. The invention additionally relates to a method for operating such a semiconductor memory.
In dynamic semiconductor memories, each of the memory cells includes a selection transistor with a storage capacitor. The storage capacitor can be connected to a bit line through the selection transistor, so that the charge content of the memory cell can be read out or written in. The selection transistor can be driven through a word line. By activation of the word line and selection of the bit line, an access is made to the memory cell disposed at the crossover of the word and bit lines. A sense amplifier is connected to the bit line so that the relatively small charge content of the memory cell is amplified by the sense amplifier to form a full-level signal and is, thus, available for further processing in the semiconductor memory.
The charge content of the storage capacitor is volatile due to the incomplete insulation of the capacitor within the integrated circuit and the leakage currents established as a result. Therefore, the charge content must be refreshed again with specific time intervals. In dynamic semiconductor memories, the operation of refreshing them again is also referred to as refresh. During the refresh, the bit line is firstly brought to an equalization level lying, for example, in the middle of the fully driven high level and low level. Afterward, as a result of the selection transistor being switched on, the capacitor of the memory cell to be refreshed is connected to the bit line. The charge content of the storage capacitor slightly displaces the equalization level of the line in accordance with the stored charge state. Such asymmetry is then amplified by the sense amplifier and subsequently output as an amplified signal onto the bit line and thereby written back again to the storage capacitor of the memory cell to be refreshed. Such an operation is likewise applied to all the other memory cells. If the quantity of charge stored in the memory cell under consideration has decreased again, the refresh operation is repeated on the memory cell.
It should be stressed that the parasitic capacitance formed by the bit line is a multiple of the relatively small capacitance of the storage capacitor of a connected memory cell. By way of example, the ratio of bit line capacitance to the capacitance of one of the memory cells amounts to 10:1. During a refresh operation, the bit line capacitance, proceeding from the equalization level, is subjected to charge reversal to a high or low level in accordance with the stored data value and is subsequently returned to the equalization level again. Due to the relatively large bit line capacitance, the current consumption brought about by these charge-reversal operations is substantially determined by the magnitude of the bit line capacitance, whereas the refreshing of the leakage current losses of the storage capacitor is pushed into the background. Thus, the power loss consumption during a refresh cycle is substantially taken up by the parasitic currents for the charge reversal of the bit line capacitances and the provision of these currents from the supply voltage.
When dynamic semiconductor memories are used in devices whose supply voltage is provided by a battery, the battery life is also limited during low-power-loss standby operation. A relatively high power loss is already consumed by the refresh cycles of the dynamic semiconductor memory. It is noticeable that the power loss consumption for the refresh is substantially brought about by the charge reversal of the parasitic bit line capacitance. The possibilities for using dynamic semiconductor memories in power-loss-critical applications are, therefore, limited.
U.S. Pat. No. 5,526,319 to Dennard et al. describes a semiconductor memory having conventional sense amplifiers and, moreover, a cyclic power source. The cyclic power source is connected to an input terminal of the sense amplifier through a switch. The switch is controlled by an enable signal so that the cyclic power source is available for reading out the data on the bit lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory with refresh and method for operating the semiconductor memory that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that has a power loss consumption as low as possible during the refresh.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory including at least one memory cell, a bit line connected to the memory cell, a sense amplifier having an output, the sense amplifier connected to the bit line, amplifying a signal read from the memory cell, and generating, at the output, an output signal derived from the signal, and an adiabatic amplifier connected to the bit line and to the output and driven by the output signal of the sense amplifier to write back the signal read from the memory cell to the memory cell in amplified form dependent upon the output signal of the sense amplifier.
The semiconductor memory has a normal operating mode, in which customary memory accesses, i.e., writing and reading of data values to and from memory cells, are carried out. Also provided is a standby operating mode with relatively low power loss consumption. During the standby operating mode, data are not input or output externally, rather all that is effected is the internal charge retention of the dynamic memory cells. During such a phase, for the purpose of carrying out the refresh operations, the adiabatic amplifier is used so that the bit line capacitances are subjected to charge reversal in a manner exhibiting a low power loss. During the low-power-loss standby operating mode, there is sufficient time available for the adiabatic amplifier to carry out an amplification operation. An amplification operation by the adiabatic amplifier takes longer than an amplification operation carried out by a normal sense amplifier.
In the case of the semiconductor memory according to the invention, an adiabatic amplifier is used for driving an amplified level onto the bit lines. A conventional characteristic of the adiabatic amplifier is that, in the event of a level transition in one direction, at least part of the reduced quantity of charge is buffer-stored in one or more capacitors and is subsequently output again in the event of a level change in the opposite direction. A level change is composed step-by-step of a plurality of charge-reversal operations into a capacitor or from a capacitor onto the circuit node to be subjected to charge reversal. Current is drawn from the supply voltage only for the final charge-reversal step so that the present level is driven fully to the supply voltage. The current consumption for traversing a level swing from the initial level to the target level and back to the initial level consumes only little current on account of the buffer-storage in capacitors. Power loss is thereby saved. Compared with conventional concepts in which the bit line is driven by an inverter, for example, more time is admittedly taken up for the charge transition from the capacitor into the circuit node to be subjected to charge reversal, the bit line in this case. Nevertheless, because there is sufficient cycle time available for a refresh cycle, the longer time duration required by an adiabatic charge-reversal operation compared with conventional concepts is not a hindrance.
Concepts for adiabatic amplifiers are described in the literature reference Luns Tee, Lizhen Zheng “Charge Recovery and Adiabatic Switching Techniques in Digital Logic”. Through the use of the adiabatic circuit concept for the charge reversal of the bit lines during a refresh cycle, power loss is substantially saved so that the semiconductor
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