Semiconductor memory with random access via two separate inputs/

Details Semiconductor memory with random access via two separate inputs/ Semiconductor memory with random access via two separate inputs/

1988-01-25

1989-08-22

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiple port access

365203, 36518904, G11C 800

Patent

active

048602639

ABSTRACT:
In a dual port RAM having separate address controls, write/read paths and pre-loading circuits for each of the two input/output terminals, conflict situations are avoided when addressing a memory cell via the address controls of both input/outputs, through use of a clock circuit (20) which respectively alternately selects the address controls (8, 10, 9, 11) and the pre-loading circuits (16, 17) so that the address control (8, 10) for the first input/output (DEA1) and the pre-loading circuit (17) for the data lines (LP.sub.P2) allocated to the second input/output (DEA2) are activated during a first clock phase, and the address control (9, 11) of the second input/output (DEA2) and the data lines (LP.sub.P1) allocated to the first input/output (DEA1) are activated during a second clock phase.

REFERENCES:
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4623990 (1986-11-01), Allen et al.
patent: 4633441 (1986-12-01), Ishimoto
IEEE Conference on Custom Integrated Circuits, Sep. 1982, pp. 311-314, S. G. Bowers, "CMOS Dual Port RAM Masterslice".

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