Semiconductor memory with pulse controlled column load circuit

Details Semiconductor memory with pulse controlled column load circuit Semiconductor memory with pulse controlled column load circuit

1978-03-22

1980-01-22

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365203, 365227, G11C 700, G11C 706

Patent

active

041853210

ABSTRACT:
A semiconductor memory device comprises a matrix array of a plurality of memory cells wherein a load circuit connected to column lines of the matrix array for charging the column lines is enabled to provide different resistance values between the actions of charging and discharging the column lines.

REFERENCES:
patent: 3932848 (1976-01-01), Porat
patent: 3969706 (1976-07-01), Proebsting et al.
Cordaro, Read--Only Storage Bit Precharge/Sense Circuit, IBM Technical Disclosure Bulletin, vol. 17, No. 4, Sep. 1974, p. 1044.

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