Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-07-23
2004-07-13
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189110, C365S228000
Reexamination Certificate
active
06762958
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor memory having a memory cell array and a multiplicity of word and bit lines and memory cells connected to the word and bit lines. The word lines can be driven by an active and a nonactive level. A control device is provided in order to cause the outputting of the nonactive level to the word lines.
Random access semiconductor memories, in particular having dynamic memory cells, so-called DRAMS (Dynamic Random Access Memories), have word lines and bit lines with memory cells arranged at their crossover points. A dynamic memory cell comprises a storage capacitor and a selection transistor. The control terminal of the selection transistor is connected to the word line. The controlled path of the selection transistor is connected to the storage capacitor at one end and to the bit line at the other end.
In the event of an access to a memory cell, for example a read access, the word line is activated by the application of an active level, so that the transistor is turned on. The storage capacitor is thereby connected to the bit line and outputs its charge onto the bit line. A sense amplifier subsequently amplifies the signal output from the storage capacitor to the bit line to form a full-level signal. The signal amplified by the sense amplifier is subsequently forwarded along the read-out data signal path as far as an output terminal, in order to be ready at the output of the semiconductor memory.
The charge content of the capacitor decreases on account of leakage currents. Therefore, the charge content in dynamic memories must be refreshed at predetermined time intervals. For this purpose, the signal amplified by the sense amplifier is written back to the memory cell via the open selection transistor. Both during the read-out and during the refresh, the word lines are activated and the amplifying operation at the sense amplifier is to be carried out until there is sufficient certainty that the read-out data value is present with a sufficiently stable level at the sense amplifier. Afterward, the activated word line can be deactivated again. In this case, a nonactive level, for example reference-ground potential or ground or even a negative level value, is output onto the word line. By contrast, the active level has a positive potential which is generated by means of voltage pumps in a manner even lying above the supply voltage fed in externally, in order that the selection transistor is completely turned on. In addition, the bit lines are precharged to an equalization level. This deactivation operation is referred to as precharge.
The correctly timed application of the nonactive level to previously selected word lines is important. If the word lines are turned off too early, so that the levels amplified on the bit lines have not yet been taken to saturation to a sufficient extent, then an only inadequately amplified signal is written back to the memory cells. The stored information is weakened as a result. In the event of a subsequent activation of such memory cells, it can happen that the stored information cannot be reestablished. On the other hand, if the turn-off of the word lines lasts too long, although there is certainty that the data signals have been amplified to a sufficiently high level, a subsequent memory access can only be effected when the word line is completely inactivated. The operating speed is reduced by a lengthy precharge operation. If the precharge operation starts too late, then precharge time is lost unnecessarily. A subsequent activation command in the same region of the memory cell array can lead, under certain circumstances, to an incorrect assessment of the cell information.
Particularly, in semiconductor memories operated clock-synchronously, so-called SDRAMs (Synchronous Dynamic Random Access Memories), the processing operations in the semiconductor memory are handled clock-synchronously, so that the precharge operation is initiated after a predetermined number of clock cycles after an activation of a memory cell. The coupling of a fixed delay time after an activation of the memory cell array for the initiation of the precharge operation has the disadvantage that the individual switching speeds of the functional elements of the semiconductor memory itself and of the entire system are not taken into account.
By way of example, a precharge operation can be initiated asynchronously after an activation of the memory cell array. For this purpose, a fixed delay time is generated on-chip for example by the charging of a capacitance. What is disadvantageous is that the exact setting of such a delay time is difficult on account of the—as is known—not inconsiderable production-dictated variation of absolute parameters of integrated components. The delay time is temperature-dependent, moreover. The current consumption caused by the charging of capacitances is not inconsiderable, moreover.
Synchronous measures count the clock pulses of the externally applied clock signal and initiate the precharge operation after a predetermined number of clock cycles have elapsed after the activation of the memory cell array. What is disadvantageous here is that the operating frequency of the semiconductor memory must be complied with as exactly as possible. If the semiconductor memory is to be operated in a relatively large operating frequency range, then it can happen at a high operating frequency that the counted clock cycles have elapsed so rapidly that the amplifying operation of the sense amplifier is not yet sufficient before the precharge operation is initiated. At a low operating frequency, it can happen that there is an unnecessarily long wait before the required number of operating clock cycles has been counted. A renewed memory access is delayed ever further in an unnecessary manner here. Furthermore, it should be taken into account that clock-synchronous semiconductor memories can co-operate with memory controllers which alter the operating frequency considerably particularly in the standby mode. These conventional concepts therefore have the disadvantage that they can either only be realized in a complex manner or cannot be adapted flexibly enough to changing operating conditions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory with precharge control, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the precharge operation is initiated at a point in time that is as optimal as possible after an access to the memory cell array, independently of the operating conditions that are currently present.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory, comprising:
a memory cell array having a multiplicity of word lines and a multiplicity of bit lines and having a multiplicity of memory cells connected to one of the word lines and one of the bit lines, the word lines having an active level, at which an access to memory cells is possible, and a nonactive or inactive level, at which an access to memory cells is not possible;
a control device in order to allocate the nonactive level to the word lines of the memory cell array;
a first and a second reference bit line, which are connected in a switchable manner to a respective terminal for a reference potential;
a comparison device, which, on the input side, is connected to at least one of the reference bit lines and, on the output side, generates a control signal depending on which the control device is caused to apply the nonactive level to the word lines.
The semiconductor memory according to the invention controls the waiting time until initiation of the precharge operation independently of the operating clock of the semiconductor memory or independently of a fixedly predetermined delay time. Rather, the precharge operation is initiated by monitoring the amplifying the operation at the pair of reference bit lines. If it is ascertained
Schneider Helmut
Schramm Achim
Auduong Gene
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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