Semiconductor memory with power-on reset controlled latched row

Details Semiconductor memory with power-on reset controlled latched row Semiconductor memory with power-on reset controlled latched row

1990-09-26

1992-06-09

Hecker, Stuart N.

Static information storage and retrieval

Powering

365227, 36523003, G11C 700

Patent

active

051213583

ABSTRACT:
An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

REFERENCES:
patent: 4104734 (1978-08-01), Herndon
patent: 4262340 (1981-04-01), Sasaki et al.
patent: 4631707 (1986-12-01), Watanabe
Wang et al., "A 21ns 32K.times.8 CMOS SRAM With a Selectively Pumped P-Well Array", Digest of Technical Papers, 1987 IEEE International Solid-State Circuits Conference (IEEE, Feb. 1987), pp. 254, 255 and 415.
Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line", IEEE Journal of Solid-State Circuits (Oct. 1984), vol. SC-19, No. 5, pp. 578-585.

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