Semiconductor memory with power-on reset control of disabled row

Details Semiconductor memory with power-on reset control of disabled row Semiconductor memory with power-on reset control of disabled row

1991-12-19

1995-06-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 365226, G11C 700

Patent

active

054249864

ABSTRACT:
An integrated circuit memory having redundant rows, for replacing a row in a primary array having a defective memory cell, is disclosed. For each primary row that is to be replaced, a fuse is opened between the output of the row decoder and the word line for the replaced row. A power-on reset circuit is provided in the memory for determining if the power supply voltage has reached an adequate voltage; if not, a transistor connected to each word line is turned on, biasing the word line to a de-energizing voltage. This ensures that the word lines for replaced rows do not power up in an "on" state.

REFERENCES:
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patent: 5250456 (1993-10-01), Bryant
Fink, et al., Electronics Engineers' Handbook, Second Edition, "Integrated Circuits and Microprocessors", (McGraw-Hill, 1982) pp. 8-98.

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