Semiconductor memory with p-channel load transistor

Details Semiconductor memory with p-channel load transistor Semiconductor memory with p-channel load transistor

1989-12-07

1990-09-04

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

365185, 365190, 365104, 365181, 307571, G11C 700, G11C 11409, G11C 1606

Patent

active

049549910

ABSTRACT:
A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

REFERENCES:
patent: 4656607 (1987-04-01), Hagiwara et al.
patent: 4663740 (1987-05-01), Ebel
patent: 4665507 (1987-05-01), Gondou et al.
patent: 4710900 (1987-12-01), Higuchi
patent: 4737936 (1988-04-01), Takeuchi
Microelectronics Digital and Analog Circuits and Systems, 1979, McGraw Hill by Jacob Millman, Ph.D., pp. 48, 49.
Frohman-Bentchkowsky, "A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory," IEEE Journal of Solid State Circuits, vol. SC-6, No. 5, pp. 301-306, Oct. 1971.

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