Semiconductor memory with load controlling feedback means to red

Details Semiconductor memory with load controlling feedback means to red Semiconductor memory with load controlling feedback means to red

1982-09-01

1986-03-25

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, 365227, G11C 700, G11C 1140

Patent

active

045787786

ABSTRACT:
A semiconductor memory circuit including a pair of feedback means. The feedback means are connected between pairs of conventional bit lines and control gates of conventional load transistors. The feedback means control the on or off state of these load transistors in accordance with the logic states of the pair of bit lines.

REFERENCES:
patent: 3983543 (1976-09-01), Cordaro
patent: 4195356 (1980-03-01), O'Connell et al.
patent: 4236229 (1980-11-01), Caudel
Anderson et al., "Memory Cell Sensing Scheme", IBM Technical Disclosure Bulletin, vol. 17, No. 6, Nov. 1974.
Konishi et al., "A 64Kb CMOS RAM", Digest of Technical Papers-IEEE International Solid State Circuits Conference, Feb. 12, 1982, pp. 258-259.
Eardley, "Static Cell Array Circuit to Enable Write by Turning Off the Cell Load Devices", IBM Tech. Disclosure Bull., vol. 24, No. 6, Nov. '81, pp. 3044-3047.

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