Semiconductor memory with inhibited test mode entry during power

Static information storage and retrieval – Read/write circuit – Testing

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365195, 365226, 365227, 371 211, 371 66, 326 16, 326 21, 326 37, 327143, G11C 700, G11C 1140

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active

054084350

ABSTRACT:
An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

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