Static information storage and retrieval – Read/write circuit – Testing
Patent
1992-11-20
1995-04-18
Harvey, Jack B.
Static information storage and retrieval
Read/write circuit
Testing
365195, 365226, 365227, 371 211, 371 66, 326 16, 326 21, 326 37, 327143, G11C 700, G11C 1140
Patent
active
054084350
ABSTRACT:
An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.
REFERENCES:
patent: 4104734 (1978-08-01), Herndon
patent: 4507761 (1985-03-01), Graham
patent: 4587640 (1986-05-01), Saitoh
patent: 4631707 (1986-12-01), Watanabe
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4734880 (1988-03-01), Collins
patent: 4755964 (1988-07-01), Miner
patent: 4771407 (1988-09-01), Takemae et al.
patent: 4777626 (1988-10-01), Matsushita
patent: 4812675 (1989-03-01), Goettting
patent: 4855621 (1989-08-01), Hoffmann et al.
patent: 4860259 (1989-08-01), Tobita
patent: 4933902 (1990-06-01), Yamada et al.
patent: 4937789 (1990-06-01), Matsubara
patent: 4942319 (1990-07-01), Pickett et al.
patent: 4956818 (1990-09-01), Hatayama et al.
patent: 4970727 (1990-11-01), Miyawaki et al.
patent: 4975883 (1990-12-01), Baker et al.
patent: 4987325 (1991-01-01), Seo
patent: 4996672 (1991-02-01), Kim
patent: 5001670 (1991-03-01), Slate et al.
patent: 5016219 (1991-05-01), Nolan et al.
patent: 5036495 (1991-07-01), Busch et al.
patent: 5047987 (1991-09-01), Kosuge
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5130645 (1992-07-01), Levy
McAdams, et al., "A 1-Nbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Journal of Solid-State Circuits (Oct. 1986), vol. SC-21, No. 5, pp. 635-642.
Shimada, et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits (Feb. 1988), vol. 23, No. 1, pp. 53-58.
Coker Thomas A.
McClure David C.
Anderson Rodney M.
Harvey Jack B.
Jorgenson Lisa K.
Lane Jack
Robinson Richard K.
LandOfFree
Semiconductor memory with inhibited test mode entry during power does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory with inhibited test mode entry during power, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with inhibited test mode entry during power will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-71082