Excavating
Patent
1990-07-13
1993-11-23
Atkinson, Charles E.
Excavating
365201, 371 681, G01R 3128
Patent
active
052651002
ABSTRACT:
An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.
REFERENCES:
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4860259 (1989-08-01), Tobita
patent: 4873669 (1989-10-01), Furutani et al.
patent: 4896322 (1990-01-01), Kraus et al.
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5072137 (1991-12-01), Slemmer
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5075892 (1991-12-01), Choy
Nishimura, et al., "A Redundancy Test-Time Reduction Technique in 1-Mbit DRAM with a Multibit Test Mode", IEEE Journal of Solid-State Circuits vol. 24, No. 1, (Feb. 1989) pp. 43-49.
McAdams, et al., "A 1-Mbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Journal of Solid-State Circuits (Oct. 1986), vol. SC-21, No. 5,, pp. 635-642.
Shimada, et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits (Feb. 1988), vol. 23, No. 1, pp. 53-58.
Coker Thomas A.
McClure David C.
Anderson Rodney M.
Atkinson Charles E.
Jorgenson Lisa K.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
LandOfFree
Semiconductor memory with improved test mode does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory with improved test mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with improved test mode will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1855496